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Participant
Participant
6,619 Views
Registered: ‎04-02-2013

Vivado 2013.4 Some IP Cores Not Linked for RTL Analysis/Synthesis

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Hi,

 

I have migrated my project from Vivado 2013.2 to 2013.4 and upgraded all the necessary IP cores. Looking at the source hierarchy, IP sources, libraries - they seem to be fine.

 

Running RTL analysis or synthesis returns the following errors:

 

[Synth 8-493] no such design unit 'clk_gen' ["C:/Users/OndrejJakubov/Projects/V3CTOR/Source/fpga/v3ctor_fpga.vhd":441]
[Synth 8-285] failed synthesizing module 'v3ctor_fpga' 

...

 

Looking at the compile order tab, I can see that some of the IP cores which are now under Block Design folder are not arranged in the compile order. clk_gen IP core is among them. There seem to be separete Design Run for these block design IPs. Does it have to do anything with it?

 

I am attaching system_stub.tcl from the design runs folder and runme.log. It looks like command read_ip is not called for clk_genand other two IP cores.

 

Many thanks!

 

Ondrej
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Participant
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10,096 Views
Registered: ‎04-02-2013

Re: Vivado 2013.4 Some IP Cores Not Linked for RTL Analysis/Synthesis

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Hi Vijay,

 

This really solved the issue! Many thanks. There are just slightly different steps to reach the point:

  1. Right click on the IP
  2. Select Out-of-Context Settings...
  3. Uncheck the IP
  4. Click OK
  5. Warning window pops up, click OK
  6. Project hieararchy updates and right click on the IP again
  7. Select Generate Output Product and OK

Cheers

Ondrej

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Participant
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Registered: ‎04-02-2013

Re: Vivado 2013.4 Some IP Cores Not Linked for RTL Analysis/Synthesis

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Additionally,

 

I can see that the three block design IP cores are compiled from verilog files, whereas the rest of my source is VHDL. Project Manager generates warnings about Duplicate Design Unit 'clk_gen' and similiar messages for the other two block design IP cores.

 

[Designutils 20-1318] Duplicate Design Unit 'clk_gen' found in library 'work' 

(Active) Duplicate found at line 75 of file "c:/Users/OndrejJakubov/Projects/V3CTOR/Source/fpga/clk/clk_gen.vhd"
Duplicate found at line 193 of file "c:/Users/OndrejJakubov/Projects/V3CTOR/Source/fpga/clk/clk_gen_funcsim.vhdl"
[Designutils 20-1318] Duplicate Design Unit 'clk_gen' found in library 'work'
(Active) Duplicate found at line 75 of file "c:/Users/OndrejJakubov/Projects/V3CTOR/Source/fpga/clk/clk_gen.vhd"
Duplicate found at line 193 of file "c:/Users/OndrejJakubov/Projects/V3CTOR/Source/fpga/clk/clk_gen_funcsim.vhdl"



 

Ondrej
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Xilinx Employee
Xilinx Employee
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Registered: ‎10-24-2013

Re: Vivado 2013.4 Some IP Cores Not Linked for RTL Analysis/Synthesis

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Hi,
Try right clicking on the IP, then Generate Output Products and then uncheck the dcp option. Generate again. This should solve the issue.
Thanks,Vijay
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Participant
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10,097 Views
Registered: ‎04-02-2013

Re: Vivado 2013.4 Some IP Cores Not Linked for RTL Analysis/Synthesis

Jump to solution

Hi Vijay,

 

This really solved the issue! Many thanks. There are just slightly different steps to reach the point:

  1. Right click on the IP
  2. Select Out-of-Context Settings...
  3. Uncheck the IP
  4. Click OK
  5. Warning window pops up, click OK
  6. Project hieararchy updates and right click on the IP again
  7. Select Generate Output Product and OK

Cheers

Ondrej

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