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Visitor ganter.ecs
Visitor
164 Views
Registered: ‎07-21-2017

Vivado 2016.2 fails rebuilding project

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I encounter a serious problem rebuilding a project again after about six month.

general info on setup:

  • SIL-4 railway project
  • Vivado 2016.2. This was the latest certified version of Vivado at development time.
  • Windows 10 Pro, latest updates August 29.
  • Kaspersky Internet Security
  • Project fully generated and built using TCL scripts.
  • Project under version control (SVN).
  • No project or tool changes since then except that Vivado 2019.1 has been installed in parallel

 

The project was successfully built about half a year ago and is being certified currently.

Yesterday I tried to rebuild the project to get some additional log and report files which are not under version control as they should be easy to regenerate. Now the build process fails. 

Here an excerpt of vivado.log:

#-----------------------------------------------------------
# Vivado v2016.2 (64-bit)
# SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016
# IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016
# Start of session at: Sun Sep 08 21:44:42 2019
# Process ID: 18188
# Current directory: X:/Baer/FPGA/P_890009_1056_ISL-8/branches/V01.04
# Command line: vivado.exe -mode batch -source make_ISL1_project.tcl
# Log file: X:/Baer/FPGA/P_890009_1056_ISL-8/branches/V01.04/vivado.log
# Journal file: X:/Baer/FPGA/P_890009_1056_ISL-8/branches/V01.04\vivado.jou
#-----------------------------------------------------------
source make_ISL1_project.tcl
# set origin_dir [file dirname [info script]]
# open_project $origin_dir/ISL1/ISL1.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2016.2/data/ip'.
# reset_run synth_1
# launch_runs synth_1 -jobs 8
INFO: [Vivado 12-4149] The synthesis checkpoint for IP 'X:/Baer/FPGA/P_890009_1056_ISL-8/branches/V01.04/source/VHDL/ip/GENERIC/SEM_IP/SEM_IP.xci' is already up-to-date
INFO: [Vivado 12-4149] The synthesis checkpoint for IP 'X:/Baer/FPGA/P_890009_1056_ISL-8/branches/V01.04/source/VHDL/ip/GENERIC/XADC_BLOCK/XADC_BLOCK.xci' is already up-to-date
[Sun Sep 08 21:44:47 2019] Launched synth_1...
Run output will be captured here: X:/Baer/FPGA/P_890009_1056_ISL-8/branches/V01.04/ISL1/ISL1.runs/synth_1/runme.log
# wait_on_run synth_1
[Sun Sep 08 21:44:47 2019] Waiting for synth_1 to finish...

*** Running vivado
with args -log ISL1.vds -m64 -mode batch -messageDb vivado.pb -notrace -source ISL1.tcl


****** Vivado v2016.2 (64-bit)
**** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016
**** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016
** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.

source ISL1.tcl -notrace
Command: synth_design -top ISL1 -part xc7a100tftg256-2 -flatten_hierarchy none
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t'
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 6100
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 288.500 ; gain = 81.125
---------------------------------------------------------------------------------

... lot of stuff spit out by synthesis deleted ...

---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:58 ; elapsed = 00:01:03 . Memory (MB): peak = 713.301 ; gain = 505.926
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 335 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:44 ; elapsed = 00:00:51 . Memory (MB): peak = 713.301 ; gain = 170.234
Synthesis Optimization Complete : Time (s): cpu = 00:00:58 ; elapsed = 00:01:03 . Memory (MB): peak = 713.301 ; gain = 505.926
INFO: [Project 1-571] Translating synthesized netlist
INFO: [Netlist 29-17] Analyzing 1802 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 2 inverter(s) to 13 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 3 instances were transformed.
OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS, OBUFDS): 3 instances

INFO: [Common 17-83] Releasing license: Synthesis
504 Infos, 109 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:01:01 ; elapsed = 00:01:04 . Memory (MB): peak = 713.301 ; gain = 500.883
report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.099 . Memory (MB): peak = 713.301 ; gain = 0.000
INFO: [Common 17-206] Exiting Vivado at Sun Sep 08 21:46:02 2019...
[Sun Sep 08 21:46:02 2019] synth_1 finished
wait_on_run: Time (s): cpu = 00:00:01 ; elapsed = 00:01:16 . Memory (MB): peak = 229.117 ; gain = 6.418
# open_run synth_1 -name synth_1
Design is defaulting to impl run constrset: constrs_1
Design is defaulting to synth run part: xc7a100tftg256-2
ERROR: [Project 1-202] Error writing the XML file 'X:/Baer/FPGA/P_890009_1056_ISL-8/branches/V01.04/ISL1/ISL1.runs/synth_1/gen_run.xml'
INFO: [Common 17-206] Exiting Vivado at Sun Sep 08 21:46:03 2019...

As can be seen the build process fails while trying to write to gen_run.xml. I found other threads describing similar problems but none of the proposed solutions helped so far:

  • reinstallation of Vivado 2016.2
  • temporarly disable antivirus, windows defender
  • delete vivado.ini
  • deinstallation of Vivado 2019.1

Interesting enough the very same project builds smoothly on a different PC so the problem definitely is not the project.
It must be a problem on my PC, an issue between Vivado, Windows and probably other applications.

Is this a known issue and is there a solution to this?

Any help highly appreciated.

 

Best regards

 

Robert

 

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1 Solution

Accepted Solutions
Visitor ganter.ecs
Visitor
94 Views
Registered: ‎07-21-2017

Re: Vivado 2016.2 fails rebuilding project

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Problem solved:

As only a few things changed between the last successful build time and when I encountered this problem there were also not many culprits to search for.
- Major Windows update: although Microsoft is well known to screw up their customers computers occasionally this was not the issue here. I write this as other users might be tempted to assume the problem here first.

- Update (renewed licence) of Internet Security software. Not the problem as there was no difference when it was disabled.

- While cleaning up the whole project structure on my local drive at the end of development I moved the whole FPGA design branch into a different location in the main project structure. This apparently lengthened the directory path to a point where Windows and/or Vivado get problems and Vivado coughs up this strange message and gives up.

It might be worth mentioning that we store all data in Truecrypt containers. So drive X: is actually a TC file. So far I could not figure out how to get kind of a "raw" path from Windows to see why it assumes it is too long. From the log it only seems to be 84 characters long which I think should definitely be no issue in a 21. century OS and/or professional software.

I was contacted yesterday by a Xilinx FAE from Avnet who proposed to mount the project with a virtual drive. Although this would have been a possible way to go I instead copied the project to a different drive which resulted in a shorter path length. The project then built successfully again. So it was definitely a problem with path length. As I simply can't imagine that a 84 character long path is too long for either Windows or Vivado (this would be too ridiculous to be true) I will further investigate if Truecrypt adds a considerable amount of path length here.

So to close this issue: if You encounter these kind of messages and problems try to shorten the path length or mount it in a virtual drive.

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3 Replies
Visitor ganter.ecs
Visitor
148 Views
Registered: ‎07-21-2017

Re: Vivado 2016.2 fails rebuilding project

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Next step tried:

- deleted all Xilinx tools completely

- renamed AppData\Roaming\Xilinx\Vivado folder to AppData\Roaming\Xilinx\Vivado.archive

- reinstalled Vivado 2016.2

- tried again to build the project. -> failed.

On a different PC (which up to date Windows 10 Pro) the whole thing works perfectly.

Honestly, I have not idea what was screwed up by whom to provoke this behaviour.

Any idea where how to solve this problem?

 

Thanks for any advice Robert

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Visitor ganter.ecs
Visitor
95 Views
Registered: ‎07-21-2017

Re: Vivado 2016.2 fails rebuilding project

Jump to solution

Problem solved:

As only a few things changed between the last successful build time and when I encountered this problem there were also not many culprits to search for.
- Major Windows update: although Microsoft is well known to screw up their customers computers occasionally this was not the issue here. I write this as other users might be tempted to assume the problem here first.

- Update (renewed licence) of Internet Security software. Not the problem as there was no difference when it was disabled.

- While cleaning up the whole project structure on my local drive at the end of development I moved the whole FPGA design branch into a different location in the main project structure. This apparently lengthened the directory path to a point where Windows and/or Vivado get problems and Vivado coughs up this strange message and gives up.

It might be worth mentioning that we store all data in Truecrypt containers. So drive X: is actually a TC file. So far I could not figure out how to get kind of a "raw" path from Windows to see why it assumes it is too long. From the log it only seems to be 84 characters long which I think should definitely be no issue in a 21. century OS and/or professional software.

I was contacted yesterday by a Xilinx FAE from Avnet who proposed to mount the project with a virtual drive. Although this would have been a possible way to go I instead copied the project to a different drive which resulted in a shorter path length. The project then built successfully again. So it was definitely a problem with path length. As I simply can't imagine that a 84 character long path is too long for either Windows or Vivado (this would be too ridiculous to be true) I will further investigate if Truecrypt adds a considerable amount of path length here.

So to close this issue: if You encounter these kind of messages and problems try to shorten the path length or mount it in a virtual drive.

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Visitor ganter.ecs
Visitor
74 Views
Registered: ‎07-21-2017

Re: Vivado 2016.2 fails rebuilding project

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Latest (and hopefully last) update:

The problem with pathes remained in the truecrypt drive, even when I moved the design to / .
Turned out the problem was in a completely different corner of Microsoft universe: No idea why but when I had created the TC container I chose NTFS as filesystem. This eventually caused these problems. Maybe Microsoft changed / tightened / whatever something on the last major update rally but apparently Vivado got locked out from accessing the drive as before.
I did not delve into the depth of access rights management of Windows 10 right now but decided to go a different way. I created another container with the same size but FAT32 FS and copied the about 50GB from the NTFS to the new container. And: wonder of wonders: all works again.

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