04-16-2018 06:25 AM - edited 04-16-2018 06:27 AM
At ferst I want to say that I read all possible topics, with the same problem as me. I tried all the proposed solutions that I found. I decided to make the topic because there are no more options ...
There is a project that has been moved from one computer to another. Version Vivado 2017.2. After opening the project, I see that the top file - non-module Files. In this case, if I press a button, create HDL wrapper, Vivado create New Wrapper, places it in the not-module Files. If I open the same project in 2014.2, everything will be in order and it will immediately determine top module file.
What I was trying to do:
1) Reinstallation of all Xilinh software.
2) Installation of 2017.3, 2017.4, 2018.1 versions
3) Disabling anti virus.
4) Removing Java (path), and other environment path.
5) Removing Microsoft Kit.
6) Run as administrator.
7) Create a simple project (and it has same error).
In general, I tested all solutions that I could find and spent this week. Therefore, I ask you for help!
Project does not have syntax error.
04-16-2018 09:15 AM
Is the generated wrapper file complete and valid or is it being generated with incorrect syntax?
Have you tried both VHDL and Verilog as the project language type? if not, what language are you using?
Are you getting any messages about srcscanner failing?
If you change the hierarchy update mode to auto update / Manual compile order (set_property source_mgmt_mode DisplayOnly [current_project]) are you able to set the wrapper to the end of the compile order and synthesize successfully?