04-16-2018 06:25 AM - edited 04-16-2018 06:27 AM
At ferst I want to say that I read all possible topics, with the same problem as me. I tried all the proposed solutions that I found. I decided to make the topic because there are no more options ...
There is a project that has been moved from one computer to another. Version Vivado 2017.2. After opening the project, I see that the top file - non-module Files. In this case, if I press a button, create HDL wrapper, Vivado create New Wrapper, places it in the not-module Files. If I open the same project in 2014.2, everything will be in order and it will immediately determine top module file.
What I was trying to do:
1) Reinstallation of all Xilinh software.
2) Installation of 2017.3, 2017.4, 2018.1 versions
3) Disabling anti virus.
4) Removing Java (path), and other environment path.
5) Removing Microsoft Kit.
6) Run as administrator.
7) Create a simple project (and it has same error).
In general, I tested all solutions that I could find and spent this week. Therefore, I ask you for help!
Project does not have syntax error.
04-16-2018 09:15 AM
Is the generated wrapper file complete and valid or is it being generated with incorrect syntax?
Have you tried both VHDL and Verilog as the project language type? if not, what language are you using?
Are you getting any messages about srcscanner failing?
If you change the hierarchy update mode to auto update / Manual compile order (set_property source_mgmt_mode DisplayOnly [current_project]) are you able to set the wrapper to the end of the compile order and synthesize successfully?
04-24-2018 01:14 AM
Thanks for the advice! I did what you said (set_property source_mgmt_mode DisplayOnly [current_project]). And generated bitstream successfully.
But the error is still the same. Top-module file is non-module... Is it ok?
I used only verilog. The project 100% does not contain an syntax error.
I did not get messages about srcscanner failing..
04-24-2018 10:07 AM
It is OK but not ideal. You are working around a problem with the Vivado source file parser.
The Vivado source file parser decides what files to send to the Synthesis process and what order to send them.
The Synthesis process does it's own parsing as well.
The workaround tells the Vivado parser not to try to figure anything out and just send all of the source files in the current order and let Synthesis figure out the correct order that things need to be parsed.
If you open the synthesized design and you see that the correct top level was chosen and there where no errors related to missing files then proceeding through bitstream generation would give you the correct design bitstream.
It would be good if you are able to submit the project to Xilinx Technical support so that we can figure out if there is something design dependent that needs to be fixed. More often than not it is that the source parser / scanner (srcscanner.exe) is just failing on a specific environment. You could still open a service request to submit information about your environment and see if you could figure out what it is that is causing srcscanner to fail.
04-24-2018 11:26 PM
All is clear, thank you. Thansk for help.
How can I provide project to support service?
This problem occurs with any project.
Even if i opened example Xilinx project. For example I choose "Open Example Project" -> "Baze Microblaze" -> "KC705".
And even in this project an error (see attachment)...
04-25-2018 12:19 PM
I've sent you a private message with a test to try. If it turns anything up, maybe we can figure what is happening on the system that is causing the file management dll to fail.
The problem seems to be with something running or something cached on the system rather than with what is installed for Xilinx or anything else on the system.