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baresi
Visitor
Visitor
196 Views
Registered: ‎04-21-2021

Vivado 2018.2 Impl ERROR: [Place 30-69], [Place 30-68], when using internal PULLUP

Hello,
I would like to transfer a VHDL design written for a Spartan 2E and translated with ISE 6.1.03i to an Artix 7.

I have translated the VHDL sources one to one with Vivado 2015.4.
Since in the old design internal PULLUPs are used (the Spartan 2E family had something like that) I got while implementing:
   INFO: [Opt 31-197] Removing PULLUP: U1I5/spislvctrPullUp[0].pullupbus
But no ERRORs.

Extract from the VHDL sources:
   component PULLUP
      port(O : out STD_LOGIC);
   end component PULLUP;
   attribute box_type : string;
   attribute box_type of PULLUP : component is "black_box";
   spislvctrPullUp: for i in 0 to 7
      generate pullupbus: PULLUP
         port map(
           O => svTxDataINT(i)
        );
      end generate spislvctrPullUp;

Now I tried to translate the same VHDL sources with Vivado 2018.2 and I get the following error messages:
   INFO: [Power 33-23] Power model is not available for spislvctrPullUp[0].pullupbus
   ERROR: [Place 30-69] Instance U1I5/spislvctrPullUp[0].pullupbus (PULLUP) is unplaced after IO placer
   ERROR: [Place 30-68] Instance U1I5/spislvctrPullUp[0].pullupbus (PULLUP) is not placed
   ERROR: [Place 30-99] Placer failed with error: 'IO Clock Placer failed'.
   ERROR: [Common 17-69] Command failed: Placer could not place all instances

Is there any way to set Vivado 2018.2 to ignore the PULLUPs (not present in the Atrix 7 family) during implementation and translate the design, as Vivado 2015.4 did?

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2 Replies
amaccre
Moderator
Moderator
114 Views
Registered: ‎04-24-2013

Hi @baresi ,

Maybe I am misunderstanding your requirements, but would removing the PULLUP component solve this for you.

You can just highlight the code, right click and toggle the line comment so that you can add it back in easily if required.

Best Regards
Aidan

 

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baresi
Visitor
Visitor
102 Views
Registered: ‎04-21-2021

Hi Moderator,

yes and no.

yes, removing the PULLUP components could solve my problem.

no, I'm using the same source code for my Spartan 2E design with ISE 6.1.03i to and for my Artix 7 design with Vivado 2018.2.
The Spartan 2E devices must have PULLUPs on the internal bidirectional databus, and that's why I do not want to change the source code.
The Artix 7 devices do not have internal PULLUPs, but with Vivado 2015.4 the PULLUPs are removed and the design works.
That's why I would like to tell the Vivado 2018.2 implementation to ignore or to remove the PULLUPs.

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