cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Advisor
Advisor
381 Views
Registered: ‎10-10-2014

Vivado 2018.3 - can no longer change address range of a bram controller with block memory generator

Jump to solution

In my current project (vivado 2018.3 with ZCU102 board as target), I tried to add a bram controller and have it auto-connect a block memory generator.

I know I have to set the memory size in the Address editor window and then validate, but somehow the drop-down box only shows 4K as an option... I tried the same in a new / empty project, and there I do get the drop-down box up to 512M. Could something have corrupted my project? or?

Here's a screenshot of the address editor window only showing 4K in the drop-down box, also my block design and IP customization dialogs:

address editor.png

bd.pngcontroller.pngmem.png

** kudo if the answer was helpful. Accept as solution if your question is answered **
0 Kudos
1 Solution

Accepted Solutions
Highlighted
Xilinx Employee
Xilinx Employee
343 Views
Registered: ‎10-01-2007

That is possible.  We have been working on a lot of address related issues lately and doing a big overhaul for 2020.1.  I can't recall every single one but this sounds like some project related issue.  Hard to tell without seeing the project itself however.

View solution in original post

3 Replies
Highlighted
Xilinx Employee
Xilinx Employee
344 Views
Registered: ‎10-01-2007

That is possible.  We have been working on a lot of address related issues lately and doing a big overhaul for 2020.1.  I can't recall every single one but this sounds like some project related issue.  Hard to tell without seeing the project itself however.

View solution in original post

Highlighted
Advisor
Advisor
312 Views
Registered: ‎10-10-2014

thanks @cdunlap for the info. I found an easy way to reproduce the issue, you can check this in 2 minutes :

1) put a Zynq US+ and AXI BRAM controller on a block design -> use connection automation

2) in the address editor : set mem size to 128k for example

3) add a 2nd AXI BRAM controller on the block design -> use connection automation

4) now in the address editor : you can only set the mem size of the 2nd controller to max 128k... as if the setting I made to the first one limits the values in the drop-down box ...

Screenshot 2020-03-13 at 17.05.47.png

note that I still can select bigger memory in controler 0:

Screenshot 2020-03-13 at 17.06.55.png

now when I change controller 0 to  512k, I can also change controller 1 to 512k, but again, not larger.

so looks like the drop-down boxes are not populated with the correct values? or there is some interaction between the 2 ...

So the workaround I use now is to unmap everything, and map everything again.

 

** kudo if the answer was helpful. Accept as solution if your question is answered **
0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
293 Views
Registered: ‎10-01-2007

I don't see this is in 2019.2 so it seems fixed already.