We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Showing results for 
Search instead for 
Did you mean: 
Newbie xpower
Registered: ‎01-28-2019

Vivado 2018.3 system wrapper update issue


I'm making a Zynq hardware (vhdl) / software project that will be placed on a subversion server and after some tests on older versions i've switched to newest Vivado 2018.3 for compability and avoiding future project restoring issues.
So i made a basis project, placed all necessary files and tcl script od SVN... and i've started to extend it.

I noticed that after adding peripherial outputs from PS on block design, after project generation, they are not added to the implementation schematic. Doing some reaserch i found out that everytime i add external / output, i have to make new system wrapper to make them visible in implementation. It seems that existing wrapper, wchich is outside of my project dir, is not beeing updated automaticly by Vivado.

The only workaround that i found for now is to make new wrapper, disable / delete the older one, and then generate bitstream on a new one.
But there's another problem... in that case i have to manualy replace older wprapper because the new is generated in Project.srcs folder by delault... and that can't be placed on server because whole Project dir (and files inside) is generated from tcl file.

Can anybody confirm this issue ? Any workaround or path for this ?
Maybee my whole design workflow is wrong ? But there was no problem on older Vivado (for ex. 2017.1).

Best regards

0 Kudos