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Explorer
Explorer
260 Views
Registered: ‎09-19-2010

Vivado 2019.1 Bug in IP Packager

Hi Guys,

I have an IP which contains 2 AXI Masters and 3 AXI Slave ports.

For each port, the IP has also a dedicated clock input.

When packaging the IP in IP Packager in vivado 2019.1 something unsual happens which to me is clearly a bug in the software.

In the ports section, obviously i need to choose the associated clock for each of the interfaces I have.

Now mysteriously, when I select the associated clock for one of my AXI Masters, the associated clocks for some other interfaces change automatically!

And then, when i fix it, vivado removes the associated clock for the AXI Master automatically.

The only way I could solve the issue was to edit the component.xml by hand.

i think this is a bug and should be addressed.

 

 

3 Replies
Moderator
Moderator
177 Views
Registered: ‎03-25-2019

Re: Vivado 2019.1 Bug in IP Packager

Hi @mamisadegh3,

Thanks for reporting this.
I could reproduce the issue locally and I have reported it internally.

Best regards,
Abdallah
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Explorer
Explorer
113 Views
Registered: ‎09-19-2010

Re: Vivado 2019.1 Bug in IP Packager

Hi,

Any update on this from Xilinx?

My ip has now 4 axi stream interfaces, 2 axi masters and 2 axi slave lite, and the issue is just getting worst.

vivado does not listen to my set associated clock commands!

Moderator
Moderator
35 Views
Registered: ‎03-25-2019

Re: Vivado 2019.1 Bug in IP Packager

Hi @mamisadegh3,

This bug has been fixed.
The fix will be available in the next release (2019.2).

Best regards,
Abdallah
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