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harryreid18
Observer
Observer
1,457 Views
Registered: ‎01-05-2019

Vivado Block Design, adding custom IP to DMA.

Hi,

I'm currently trying to build a block design that incorporates a custom IP block created in HLS and a DMA interface & FIFO stream. I am very new to this subject and an unsure where to connect the custom IP block. The block itself will obtain two inputs from the DMA and send one output back to the DMA. Here is my current block design (without the custom IP). 

blockdesign.pngIf I had to guess it would be connected to the DMA somehow but again I really am unsure. I've tried to search for something similar but cannot find anything.

 

Thanks in advance.

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3 Replies
tedbooth
Scholar
Scholar
1,426 Views
Registered: ‎03-28-2016

Step number 1 is to develop your custom HLS IP to use AXI4-Stream inputs and outputs.  Look in UG902 for more details on AXI4-Stream Interfaces.

Once your IP has AXI4-Stream interfaces, the output AXI4-Stream port will connect to the "S_AXIS_S2MM" port on the DMA.  The input AXI4-Stream port will connect to the "M_AXIS_MM2S" port on the DMA.  If you have more than one input or output then you will need more DMAs.  One DMA can only support 1 input and 1 output.

Ted Booth | Tech. Lead FPGA Design Engineer | DesignLinx Solutions
https://www.designlinxhs.com
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harryreid18
Observer
Observer
1,422 Views
Registered: ‎01-05-2019

Brilliant thank you Ted I will look into this.

I have tried implementing another DMA into the design as you have suggested here:blkdesign1.pngHowever I am getting some critical warnings when I try to validate it:

warnings.png

It is saying that the DMA slaves are not mapped to the processing system however they are connected via the interconnect. Would you happen to know what the issue is here? 

 

Thanks again!

 

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kenryan2
Explorer
Explorer
1,367 Views
Registered: ‎04-22-2015

Go to the "Address Editor" tab in the block design page and look for "Unmapped Slaves".  Right-click, select "Auto Assign Address", the tools will assign addresses to each IP not currently mapped.  Note this is for the control/status register port of the DMA block.

I suggest at least reading through UG940 "Vivado Design Suite Tutorial: Embedded Processor Hardware Design".  It includes examples of all of these steps.

ken

 

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