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Visitor aocg72
Visitor
6,627 Views
Registered: ‎11-14-2016

Vivado: Block Design error when a RTL block instantiates catalog IP

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Hi,


I'm encountering an odd error when I attempt to instantiate a catalog IP within a (Verilog) RTL block, but only if the RTL block is part of a Block design.

 

I'm using Vivado v2016.4 (64-bit).


A minimal design demonstrating the error:

 

1) New project, create an empty Block Design.

 

2) Create new Verilog source file ('rtlwrapper.v'):

 

module rtlwrapper(
input clock,
output [15:0] count
);
endmodule

 

3) Add 'rtlwrapper.v' to Block Design.

 

4) In Block design, make the signals of the new RTL block external.

 

5) Generate Output Products and HDL Wrapper for 'blockdesign'.

 

6) In the IP Catalog, customize a Binary Counter with default settings (16bits wide).

 

7) Instantiate the counter IP in 'rtlwrapper.v':

 

module rtlwrapper(
    input clock,
    output [15:0] count
);

c_counter_binary_0 counter_instance (
    .CLK(clk), // input wire CLK
    .Q(count) // output wire [3 : 0] Q
);

endmodule

 

 

8) As soon as that's saved, a notification appears: "Module references are out-of-date. Refresh...".

 

9) Refreshing pops up this critical error:

 

[filemgmt 56-181] Reference 'rtlwrapper' contains sub-design file '/DATA0/iwo/Research/fpga/iptest/iptest.srcs/sources_1/ip/c_counter_binary_0/c_counter_binary_0.xci'. This sub-design is not allowed in the reference due to following reason(s):
IP references are currently not enabled.

 

Is there a setting somewhere to enable "IP references"?


All the following alternative scenarios work fine:

 

- instantiating modules that are not originating in the IP Catalog (other Verilog files).

- using 'rtlwrapper.v' (including the IP instance) as the top-level module.

- inserting the IP directly into the Block Design

- packaging 'rtlwrapper.v' (including the counter IP instance) as IP itself and adding that to the Block Design.

 

The last method allows me to synthesize the design, but requires a cumbersome design flow. Any change in the lowest level has to be propagated through several IP projects to the top.

 

I'd like to enter a design that is a Block Design at the top level, with HDL RTL blocks that include more IP themselves. Ideally without packaging everything as IP, all the way down.

 

Is there a more elegant design flow that I'm missing?

 


Best regards,

 

Iwo

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1 Solution

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Moderator
Moderator
11,249 Views
Registered: ‎07-21-2014

Re: Vivado: Block Design error when a RTL block instantiates catalog IP

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@aocg72

 

As explained by @florentw, the best way to achieve this is by using custom IP. Package the design as an IP and then import into the BD. As per my understanding the flow you are using will need more efforts and manual work as compare to the custom IP flow.

 

Thanks,
Anusheel
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Moderator
Moderator
6,617 Views
Registered: ‎07-21-2014

Re: Vivado: Block Design error when a RTL block instantiates catalog IP

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@aocg72

 

Please correct me if my understanding is not correct. You are using "Add Module" to add a RTL file in the block design and then you are editing it in order to instantiate an IP. I think this flow is as good as adding IP in the block design directly.

 

However, this flow is not supported. The modules which are supported with "Add Module" should not have any XCI definition, please check UG994 for more details.

 

Capture.PNG

 

Thanks,
Anusheel
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Xilinx Employee
Xilinx Employee
6,611 Views
Registered: ‎08-01-2008

Re: Vivado: Block Design error when a RTL block instantiates catalog IP

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check this ARs
https://www.xilinx.com/support/answers/57546.html
Thanks and Regards
Balkrishan
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Visitor aocg72
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6,603 Views
Registered: ‎11-14-2016

Re: Vivado: Block Design error when a RTL block instantiates catalog IP

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Thanks.

You are correct, in the example I gave there is no difference between adding the IP directly to the Block Design and instantiating it first in Verilog.

My real problem is more complex, however, with many levels of Verilog and several IP blocks instantiated.

I'd have to pass all the IP interconnect back to the top level, which would be painful.

I'll go and read the documentation you pointed me at in more detail.

Best regards,

Iwo
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Moderator
Moderator
6,596 Views
Registered: ‎11-09-2015

Re: Vivado: Block Design error when a RTL block instantiates catalog IP

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Hi @aocg72,

 

"You are correct, in the example I gave there is no difference between adding the IP directly to the Block Design and instantiating it first in Verilog."

 

I think what @anusheel meant is that you should package your Verilog file in an IP and then add it as an IP to your BD. Then for you it will be quite the same.

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
Moderator
11,250 Views
Registered: ‎07-21-2014

Re: Vivado: Block Design error when a RTL block instantiates catalog IP

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@aocg72

 

As explained by @florentw, the best way to achieve this is by using custom IP. Package the design as an IP and then import into the BD. As per my understanding the flow you are using will need more efforts and manual work as compare to the custom IP flow.

 

Thanks,
Anusheel
-----------------------------------------------------------------------------------------------
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View solution in original post

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Visitor aocg72
Visitor
6,535 Views
Registered: ‎11-14-2016

Re: Vivado: Block Design error when a RTL block instantiates catalog IP

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Thanks to all for your help. I now understand that what I want can only be done by turning my HDL into IP first.

Are there plans to change that in a future release?

For what it's worth, I tried the same thing in ISE 13.1 - IP instantiated in HDL, HDL wrapped in a symbol used in a schematic. Works fine.

Best regards,

Iwo
Moderator
Moderator
6,522 Views
Registered: ‎11-09-2015

Re: Vivado: Block Design error when a RTL block instantiates catalog IP

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Hi @aocg72,

 

I guess at some point Vivado will support that. But I don't know for a precise release.

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Contributor
Contributor
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Registered: ‎03-17-2017

Re: Vivado: Block Design error when a RTL block instantiates catalog IP

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Just a note to everyone, I've noticed the same behavior if you try to use the XPM's (Xilinx Parameterized Modules) inside of a verilog wrapper file and bring them into a block design. Only way to make that work is to package the XPM as its own project and then use the generated IP from the repository. Would be great if Vivado was updated to support .XCI and XPM contents without having to package every little block that's needed.

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