07-01-2019 11:42 PM
I hope I'm posting to the right forum, but here goes:
In Vivado 2016.4: I am trying to place a VHDL module into a block diagram and that VHDL module includes Xilinx IP. I am getting an error:
ERROR: [filemgmt 56-181] Reference 'TOP_<NAME_OF_MODULE>' contains sub-design file 'D:/.../_ip/BLK_MEM_SP_8B/BLK_MEM_SP_8B.xci'. This sub-design is not allowed in the reference due to following reason(s): IP references are currently not enabled.
So it seems that my big block of logic that contains a bunch of Xilinx IP blocks (RAM, MCMM, initialized ROM, etc) can't be placed in the block diagram and hooked up to the Zynq processor... Isn't this a major flaw in the whole FPGA fabric design concept? Maybe I can "enable" IP references, as the end of the error message might imply? What gives?
- Cheers, Sam
//Microsemi's Libero has no similar problem hangup. I don't know about Quartus...
07-02-2019 12:34 AM
Check XCI Inferencing topic in below link at page 221:
You can package your block which has xci file in it using Vivado IP packager feature and add the custom IP in your block design:
07-04-2019 01:02 PM
Wow. This is incomprehensibly difficult. I got it placed by
(1) deactivating all unused items in my project other than the RTL module
(2) packaging RTL into IP.
I tried other ways, it didn't work. I appreciate the pointers to documentation, but I am NOT going to read 100 pages of Xilinx garbage. Unfortunately, if this exercise has taught me anything, it is that the Zynq and Vivado are over-designed for nearly all my purposes, and stupidly complicated. It took deleting and rebuilding entire IP packages just to upgrade them. I mean, this is horrendous. I will never recommend Zynq on a platform, ever.