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Explorer
Explorer
9,796 Views
Registered: ‎01-09-2012

Vivado ELABORATE_PROC

I currently try to port an EDK pcore (PLB4.6) to Vivado (AXI) and I can not find any appropriate replacement for: "OPTION ELABORATE_PROC"

What I am trying to port from EDK to Vivado is a component which takes at elaboration the system date/time and copyies this date and time as generics into my component and allows me to read the core compilation date/time by a bus access. Basically it would be fine if the IP component in Vivado would have some TCL call to a user script whicht updates some generic parameters before synthesis (at elaboration phase would pe perfect.).

 

In EDK ELABORATE_PROC is doing the following:

Defines the Tcl entry point for the IP core’s elaboration. This procedure is run after Platgen completes the merge of MPD and MHS descriptions, and it is suitable for use in Tcl to generate VHDL/VERILOG for the IP core being elaborated.
It is expressed in the following format: OPTION ELABORATE_PROC = proc_name

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7 Replies
Teacher muzaffer
Teacher
9,782 Views
Registered: ‎03-31-2012

Re: Vivado ELABORATE_PROC

In Vivado gui, there is an option to call a tcl script before synthesis: synthesis settings, tcl.pre. You should be able to set a global parameter which your component will use for time/date. It's certainly doable in (s)verilog but not sure how in VHDL.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
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Explorer
Explorer
9,745 Views
Registered: ‎01-09-2012

Re: Vivado ELABORATE_PROC

Hello muzaffer

 

Hm, the "tcl.pre" in the synthesis options appears not to be called in in a synthesis run of  Vivado 2015.2... at least I do not see it in the log file... it looks like its not being called. The generics in VHDL I managed to load by following script:

 

proc date_generate {} {

   puts "Compilation date and time is set to:"

   set date_raw     [clock seconds]
   set cell_handle [get_cells {*/version_date_inst/U0}]

   set c_date [clock format $date_raw -format %Y]
   scan $c_date "%d" c_date_int
   set_property C_DATE_YEAR [expr $c_date_int] $cell_handle
   puts "C_DATE_YEAR   : $c_date_int"

   set c_date [clock format $date_raw -format %m]
   scan $c_date "%d" c_date_int
   set_property C_DATE_MONTH [expr $c_date_int] $cell_handle
   puts "C_DATE_MONTH  : $c_date_int"

   set c_date [clock format $date_raw -format %e]
   scan $c_date "%d" c_date_int
   set_property C_DATE_DAY [expr $c_date_int] $cell_handle
   puts "C_DATE_DAY    : $c_date_int"

   set c_date [clock format $date_raw -format %k]
   scan $c_date "%d" c_date_int
   set_property C_DATE_HOUR [expr $c_date_int] $cell_handle
   puts "C_DATE_HOUR   : $c_date_int"

   set c_date [clock format $date_raw -format %M]
   scan $c_date "%d" c_date_int
   set_property C_DATE_MINUTE [expr $c_date_int] $cell_handle
   puts "C_DATE_MINUTE : $c_date_int"

   return
}

 

Now all needed is this date_generate.tcl being called by Vivado. Lets hope I do not need to invest days in such a simple thing.

 

 

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Teacher muzaffer
Teacher
9,740 Views
Registered: ‎03-31-2012

Re: Vivado ELABORATE_PROC

did you open up the synthesis settings and added your function there by selecting from the file select dialog? also I think your script actually has to call your function. just having the proc is not enough.

 

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Explorer
Explorer
9,641 Views
Registered: ‎01-09-2012

Re: Vivado ELABORATE_PROC

Hello and good morning muzaffer,

 

Yes I added the tcl in the synthesis options:

 

Capture.PNG

 

And in the synthesis log I find:

...

source soc_wrapper.tcl -notrace
source C:/temp/G/GPAC/Board/GPAC3_0/SYS_FPGA/SwissFEL_CAV/date_generate.tcl
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/temp/G/GPAC/Lib/Vivado_Lib/version_date_1.0'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/sw/Xilinx/Vivado/2015.2/data/ip'.

...

 

Hence I assume Vivado got the date_generate.tcl from tcl.pre as it should... unfortunately I have no infos what Vivado does with this "date_generate.tcl". I do not see this script ever being called in the synthesis log.

 

Later in the synthesis log  can find the lines which prove that the "date_generate.tcl" was never called:

...

INFO: [Synth 8-638] synthesizing module 'soc_version_date_inst_0' [c:/temp/G/GPAC/Board/GPAC3_0/SYS_FPGA/SwissFEL_CAV/soc.srcs/sources_1/bd/soc/ip/soc_version_date_inst_0/synth/soc_version_date_inst_0.vhd:98]
    Parameter C_VERSION bound to: 32'b00000001000000101011111010101111
    Parameter C_VERSION_MAJOR bound to: bla_project - type: string
    Parameter C_VERSION_MINOR bound to: bla_machine - type: string
    Parameter C_DATE_YEAR bound to: 0 - type: integer
    Parameter C_DATE_MONTH bound to: 0 - type: integer
    Parameter C_DATE_DAY bound to: 0 - type: integer
    Parameter C_DATE_HOUR bound to: 0 - type: integer
    Parameter C_DATE_MINUTE bound to: 0 - type: integer
    Parameter C_S00_AXI_ID_WIDTH bound to: 0 - type: integer
    Parameter C_S00_AXI_DATA_WIDTH bound to: 32 - type: integer
    Parameter C_S00_AXI_ADDR_WIDTH bound to: 8 - type: integer
    Parameter C_S00_AXI_ARUSER_WIDTH bound to: 0 - type: integer
    Parameter C_S00_AXI_RUSER_WIDTH bound to: 0 - type: integer
    Parameter C_S00_AXI_AWUSER_WIDTH bound to: 0 - type: integer
    Parameter C_S00_AXI_WUSER_WIDTH bound to: 0 - type: integer
    Parameter C_S00_AXI_BUSER_WIDTH bound to: 0 - type: integer
INFO: [Synth 8-638] synthesizing module 'version_date_v1_0' [c:/temp/G/GPAC/Board/GPAC3_0/SYS_FPGA/SwissFEL_CAV/soc.srcs/sources_1/ipshared/psi.ch/version_date_v1_0/abf1293a/hdl/version_date_v1_0.vhd:103]
    Parameter C_VERSION bound to: 16957103 - type: integer
    Parameter C_VERSION_MAJOR bound to: bla_project - type: string
    Parameter C_VERSION_MINOR bound to: bla_machine - type: string
    Parameter C_DATE_YEAR bound to: 0 - type: integer
    Parameter C_DATE_MONTH bound to: 0 - type: integer
    Parameter C_DATE_DAY bound to: 0 - type: integer
    Parameter C_DATE_HOUR bound to: 0 - type: integer
    Parameter C_DATE_MINUTE bound to: 0 - type: integer
    Parameter C_S00_AXI_ID_WIDTH bound to: 0 - type: integer
    Parameter C_S00_AXI_DATA_WIDTH bound to: 32 - type: integer
    Parameter C_S00_AXI_ADDR_WIDTH bound to: 8 - type: integer
    Parameter C_S00_AXI_ARUSER_WIDTH bound to: 0 - type: integer
    Parameter C_S00_AXI_RUSER_WIDTH bound to: 0 - type: integer
    Parameter C_S00_AXI_AWUSER_WIDTH bound to: 0 - type: integer
    Parameter C_S00_AXI_WUSER_WIDTH bound to: 0 - type: integer
    Parameter C_S00_AXI_BUSER_WIDTH bound to: 0 - type: integer
WARNING: [Synth 8-506] null port 's00_axi_arid' ignored [c:/temp/G/GPAC/Board/GPAC3_0/SYS_FPGA/SwissFEL_CAV/soc.srcs/sources_1/ipshared/psi.ch/version_date_v1_0/abf1293a/hdl/version_date_v1_0.vhd:52]
WARNING: [Synth 8-506] null port 's00_axi_aruser' ignored [c:/temp/G/GPAC/Board/GPAC3_0/SYS_FPGA/SwissFEL_CAV/soc.srcs/sources_1/ipshared/psi.ch/version_date_v1_0/abf1293a/hdl/version_date_v1_0.vhd:62]
WARNING: [Synth 8-506] null port 's00_axi_rid' ignored [c:/temp/G/GPAC/Board/GPAC3_0/SYS_FPGA/SwissFEL_CAV/soc.srcs/sources_1/ipshared/psi.ch/version_date_v1_0/abf1293a/hdl/version_date_v1_0.vhd:66]
WARNING: [Synth 8-506] null port 's00_axi_ruser' ignored [c:/temp/G/GPAC/Board/GPAC3_0/SYS_FPGA/SwissFEL_CAV/soc.srcs/sources_1/ipshared/psi.ch/version_date_v1_0/abf1293a/hdl/version_date_v1_0.vhd:70]
WARNING: [Synth 8-506] null port 's00_axi_awid' ignored [c:/temp/G/GPAC/Board/GPAC3_0/SYS_FPGA/SwissFEL_CAV/soc.srcs/sources_1/ipshared/psi.ch/version_date_v1_0/abf1293a/hdl/version_date_v1_0.vhd:74]
WARNING: [Synth 8-506] null port 's00_axi_awuser' ignored [c:/temp/G/GPAC/Board/GPAC3_0/SYS_FPGA/SwissFEL_CAV/soc.srcs/sources_1/ipshared/psi.ch/version_date_v1_0/abf1293a/hdl/version_date_v1_0.vhd:84]
WARNING: [Synth 8-506] null port 's00_axi_wuser' ignored [c:/temp/G/GPAC/Board/GPAC3_0/SYS_FPGA/SwissFEL_CAV/soc.srcs/sources_1/ipshared/psi.ch/version_date_v1_0/abf1293a/hdl/version_date_v1_0.vhd:91]
WARNING: [Synth 8-506] null port 's00_axi_bid' ignored [c:/temp/G/GPAC/Board/GPAC3_0/SYS_FPGA/SwissFEL_CAV/soc.srcs/sources_1/ipshared/psi.ch/version_date_v1_0/abf1293a/hdl/version_date_v1_0.vhd:95]
WARNING: [Synth 8-506] null port 's00_axi_buser' ignored [c:/temp/G/GPAC/Board/GPAC3_0/SYS_FPGA/SwissFEL_CAV/soc.srcs/sources_1/ipshared/psi.ch/version_date_v1_0/abf1293a/hdl/version_date_v1_0.vhd:97]
    Parameter C_VERSION bound to: 16957103 - type: integer
    Parameter C_VERSION_MAJOR bound to: bla_project - type: string
    Parameter C_VERSION_MINOR bound to: bla_machine - type: string
    Parameter C_DATE_YEAR bound to: 0 - type: integer
    Parameter C_DATE_MONTH bound to: 0 - type: integer
    Parameter C_DATE_DAY bound to: 0 - type: integer
    Parameter C_DATE_HOUR bound to: 0 - type: integer
    Parameter C_DATE_MINUTE bound to: 0 - type: integer
    Parameter C_S_AXI_ID_WIDTH bound to: 0 - type: integer
    Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
    Parameter C_S_AXI_ADDR_WIDTH bound to: 8 - type: integer
    Parameter C_S_AXI_ARUSER_WIDTH bound to: 0 - type: integer
    Parameter C_S_AXI_RUSER_WIDTH bound to: 0 - type: integer
    Parameter C_S_AXI_AWUSER_WIDTH bound to: 0 - type: integer
    Parameter C_S_AXI_WUSER_WIDTH bound to: 0 - type: integer
    Parameter C_S_AXI_BUSER_WIDTH bound to: 0 - type: integer
WARNING: [Synth 8-506] null port 's_axi_arid' ignored [c:/temp/G/GPAC/Board/GPAC3_0/SYS_FPGA/SwissFEL_CAV/soc.srcs/sources_1/ipshared/psi.ch/version_date_v1_0/abf1293a/hdl/version_date_v1_0.vhd:137]
WARNING: [Synth 8-506] null port 's_axi_aruser' ignored [c:/temp/G/GPAC/Board/GPAC3_0/SYS_FPGA/SwissFEL_CAV/soc.srcs/sources_1/ipshared/psi.ch/version_date_v1_0/abf1293a/hdl/version_date_v1_0.vhd:147]
WARNING: [Synth 8-506] null port 's_axi_rid' ignored [c:/temp/G/GPAC/Board/GPAC3_0/SYS_FPGA/SwissFEL_CAV/soc.srcs/sources_1/ipshared/psi.ch/version_date_v1_0/abf1293a/hdl/version_date_v1_0.vhd:151]
WARNING: [Synth 8-506] null port 's_axi_ruser' ignored [c:/temp/G/GPAC/Board/GPAC3_0/SYS_FPGA/SwissFEL_CAV/soc.srcs/sources_1/ipshared/psi.ch/version_date_v1_0/abf1293a/hdl/version_date_v1_0.vhd:155]
WARNING: [Synth 8-506] null port 's_axi_awid' ignored [c:/temp/G/GPAC/Board/GPAC3_0/SYS_FPGA/SwissFEL_CAV/soc.srcs/sources_1/ipshared/psi.ch/version_date_v1_0/abf1293a/hdl/version_date_v1_0.vhd:159]
WARNING: [Synth 8-506] null port 's_axi_awuser' ignored [c:/temp/G/GPAC/Board/GPAC3_0/SYS_FPGA/SwissFEL_CAV/soc.srcs/sources_1/ipshared/psi.ch/version_date_v1_0/abf1293a/hdl/version_date_v1_0.vhd:169]
WARNING: [Synth 8-506] null port 's_axi_wuser' ignored [c:/temp/G/GPAC/Board/GPAC3_0/SYS_FPGA/SwissFEL_CAV/soc.srcs/sources_1/ipshared/psi.ch/version_date_v1_0/abf1293a/hdl/version_date_v1_0.vhd:176]
WARNING: [Synth 8-506] null port 's_axi_bid' ignored [c:/temp/G/GPAC/Board/GPAC3_0/SYS_FPGA/SwissFEL_CAV/soc.srcs/sources_1/ipshared/psi.ch/version_date_v1_0/abf1293a/hdl/version_date_v1_0.vhd:180]
WARNING: [Synth 8-506] null port 's_axi_buser' ignored [c:/temp/G/GPAC/Board/GPAC3_0/SYS_FPGA/SwissFEL_CAV/soc.srcs/sources_1/ipshared/psi.ch/version_date_v1_0/abf1293a/hdl/version_date_v1_0.vhd:182]
INFO: [Synth 8-638] synthesizing module 'version_date_v1_0_user' [c:/temp/G/GPAC/Board/GPAC3_0/SYS_FPGA/SwissFEL_CAV/soc.srcs/sources_1/ipshared/psi.ch/version_date_v1_0/abf1293a/hdl/version_date_v1_0_user.vhd:103]
    Parameter C_VERSION bound to: 16957103 - type: integer
    Parameter C_VERSION_MAJOR bound to: bla_project - type: string
    Parameter C_VERSION_MINOR bound to: bla_machine - type: string
    Parameter C_DATE_YEAR bound to: 0 - type: integer
    Parameter C_DATE_MONTH bound to: 0 - type: integer
    Parameter C_DATE_DAY bound to: 0 - type: integer
    Parameter C_DATE_HOUR bound to: 0 - type: integer
    Parameter C_DATE_MINUTE bound to: 0 - type: integer
    Parameter C_S_AXI_ID_WIDTH bound to: 0 - type: integer
    Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
    Parameter C_S_AXI_ADDR_WIDTH bound to: 8 - type: integer
    Parameter C_S_AXI_ARUSER_WIDTH bound to: 0 - type: integer
    Parameter C_S_AXI_RUSER_WIDTH bound to: 0 - type: integer
    Parameter C_S_AXI_AWUSER_WIDTH bound to: 0 - type: integer
    Parameter C_S_AXI_WUSER_WIDTH bound to: 0 - type: integer
    Parameter C_S_AXI_BUSER_WIDTH bound to: 0 - type: integer
WARNING: [Synth 8-506] null port 's_axi_arid' ignored [c:/temp/G/GPAC/Board/GPAC3_0/SYS_FPGA/SwissFEL_CAV/soc.srcs/sources_1/ipshared/psi.ch/version_date_v1_0/abf1293a/hdl/version_date_v1_0_user.vhd:52]
WARNING: [Synth 8-506] null port 's_axi_aruser' ignored [c:/temp/G/GPAC/Board/GPAC3_0/SYS_FPGA/SwissFEL_CAV/soc.srcs/sources_1/ipshared/psi.ch/version_date_v1_0/abf1293a/hdl/version_date_v1_0_user.vhd:62]
WARNING: [Synth 8-506] null port 's_axi_rid' ignored [c:/temp/G/GPAC/Board/GPAC3_0/SYS_FPGA/SwissFEL_CAV/soc.srcs/sources_1/ipshared/psi.ch/version_date_v1_0/abf1293a/hdl/version_date_v1_0_user.vhd:66]
WARNING: [Synth 8-506] null port 's_axi_ruser' ignored [c:/temp/G/GPAC/Board/GPAC3_0/SYS_FPGA/SwissFEL_CAV/soc.srcs/sources_1/ipshared/psi.ch/version_date_v1_0/abf1293a/hdl/version_date_v1_0_user.vhd:70]
WARNING: [Synth 8-506] null port 's_axi_awid' ignored [c:/temp/G/GPAC/Board/GPAC3_0/SYS_FPGA/SwissFEL_CAV/soc.srcs/sources_1/ipshared/psi.ch/version_date_v1_0/abf1293a/hdl/version_date_v1_0_user.vhd:74]
WARNING: [Synth 8-506] null port 's_axi_awuser' ignored [c:/temp/G/GPAC/Board/GPAC3_0/SYS_FPGA/SwissFEL_CAV/soc.srcs/sources_1/ipshared/psi.ch/version_date_v1_0/abf1293a/hdl/version_date_v1_0_user.vhd:84]
WARNING: [Synth 8-506] null port 's_axi_wuser' ignored [c:/temp/G/GPAC/Board/GPAC3_0/SYS_FPGA/SwissFEL_CAV/soc.srcs/sources_1/ipshared/psi.ch/version_date_v1_0/abf1293a/hdl/version_date_v1_0_user.vhd:91]
WARNING: [Synth 8-506] null port 's_axi_bid' ignored [c:/temp/G/GPAC/Board/GPAC3_0/SYS_FPGA/SwissFEL_CAV/soc.srcs/sources_1/ipshared/psi.ch/version_date_v1_0/abf1293a/hdl/version_date_v1_0_user.vhd:95]
WARNING: [Synth 8-506] null port 's_axi_buser' ignored [c:/temp/G/GPAC/Board/GPAC3_0/SYS_FPGA/SwissFEL_CAV/soc.srcs/sources_1/ipshared/psi.ch/version_date_v1_0/abf1293a/hdl/version_date_v1_0_user.vhd:97]
WARNING: [Synth 8-3919] null assignment ignored [c:/temp/G/GPAC/Board/GPAC3_0/SYS_FPGA/SwissFEL_CAV/soc.srcs/sources_1/ipshared/psi.ch/version_date_v1_0/abf1293a/hdl/version_date_v1_0_user.vhd:125]
WARNING: [Synth 8-3919] null assignment ignored [c:/temp/G/GPAC/Board/GPAC3_0/SYS_FPGA/SwissFEL_CAV/soc.srcs/sources_1/ipshared/psi.ch/version_date_v1_0/abf1293a/hdl/version_date_v1_0_user.vhd:250]
WARNING: [Synth 8-3919] null assignment ignored [c:/temp/G/GPAC/Board/GPAC3_0/SYS_FPGA/SwissFEL_CAV/soc.srcs/sources_1/ipshared/psi.ch/version_date_v1_0/abf1293a/hdl/version_date_v1_0_user.vhd:253]
WARNING: [Synth 8-3919] null assignment ignored [c:/temp/G/GPAC/Board/GPAC3_0/SYS_FPGA/SwissFEL_CAV/soc.srcs/sources_1/ipshared/psi.ch/version_date_v1_0/abf1293a/hdl/version_date_v1_0_user.vhd:368]
WARNING: [Synth 8-3919] null assignment ignored [c:/temp/G/GPAC/Board/GPAC3_0/SYS_FPGA/SwissFEL_CAV/soc.srcs/sources_1/ipshared/psi.ch/version_date_v1_0/abf1293a/hdl/version_date_v1_0_user.vhd:370]
WARNING: [Synth 8-3848] Net slv_reg_rd[11] in module/entity version_date_v1_0_user does not have driver. [c:/temp/G/GPAC/Board/GPAC3_0/SYS_FPGA/SwissFEL_CAV/soc.srcs/sources_1/ipshared/psi.ch/version_date_v1_0/abf1293a/hdl/version_date_v1_0_user.vhd:149]
WARNING: [Synth 8-3848] Net slv_reg_rd[12] in module/entity version_date_v1_0_user does not have driver. [c:/temp/G/GPAC/Board/GPAC3_0/SYS_FPGA/SwissFEL_CAV/soc.srcs/sources_1/ipshared/psi.ch/version_date_v1_0/abf1293a/hdl/version_date_v1_0_user.vhd:149]
WARNING: [Synth 8-3848] Net slv_reg_rd[13] in module/entity version_date_v1_0_user does not have driver. [c:/temp/G/GPAC/Board/GPAC3_0/SYS_FPGA/SwissFEL_CAV/soc.srcs/sources_1/ipshared/psi.ch/version_date_v1_0/abf1293a/hdl/version_date_v1_0_user.vhd:149]
WARNING: [Synth 8-3848] Net slv_reg_rd[14] in module/entity version_date_v1_0_user does not have driver. [c:/temp/G/GPAC/Board/GPAC3_0/SYS_FPGA/SwissFEL_CAV/soc.srcs/sources_1/ipshared/psi.ch/version_date_v1_0/abf1293a/hdl/version_date_v1_0_user.vhd:149]
WARNING: [Synth 8-3848] Net slv_reg_rd[15] in module/entity version_date_v1_0_user does not have driver. [c:/temp/G/GPAC/Board/GPAC3_0/SYS_FPGA/SwissFEL_CAV/soc.srcs/sources_1/ipshared/psi.ch/version_date_v1_0/abf1293a/hdl/version_date_v1_0_user.vhd:149]
WARNING: [Synth 8-3848] Net slv_reg_rd[19] in module/entity version_date_v1_0_user does not have driver. [c:/temp/G/GPAC/Board/GPAC3_0/SYS_FPGA/SwissFEL_CAV/soc.srcs/sources_1/ipshared/psi.ch/version_date_v1_0/abf1293a/hdl/version_date_v1_0_user.vhd:149]
WARNING: [Synth 8-3848] Net slv_reg_rd[23] in module/entity version_date_v1_0_user does not have driver. [c:/temp/G/GPAC/Board/GPAC3_0/SYS_FPGA/SwissFEL_CAV/soc.srcs/sources_1/ipshared/psi.ch/version_date_v1_0/abf1293a/hdl/version_date_v1_0_user.vhd:149]
WARNING: [Synth 8-3848] Net slv_reg_rd[24] in module/entity version_date_v1_0_user does not have driver. [c:/temp/G/GPAC/Board/GPAC3_0/SYS_FPGA/SwissFEL_CAV/soc.srcs/sources_1/ipshared/psi.ch/version_date_v1_0/abf1293a/hdl/version_date_v1_0_user.vhd:149]
WARNING: [Synth 8-3848] Net slv_reg_rd[25] in module/entity version_date_v1_0_user does not have driver. [c:/temp/G/GPAC/Board/GPAC3_0/SYS_FPGA/SwissFEL_CAV/soc.srcs/sources_1/ipshared/psi.ch/version_date_v1_0/abf1293a/hdl/version_date_v1_0_user.vhd:149]
WARNING: [Synth 8-3848] Net slv_reg_rd[26] in module/entity version_date_v1_0_user does not have driver. [c:/temp/G/GPAC/Board/GPAC3_0/SYS_FPGA/SwissFEL_CAV/soc.srcs/sources_1/ipshared/psi.ch/version_date_v1_0/abf1293a/hdl/version_date_v1_0_user.vhd:149]
WARNING: [Synth 8-3848] Net slv_reg_rd[27] in module/entity version_date_v1_0_user does not have driver. [c:/temp/G/GPAC/Board/GPAC3_0/SYS_FPGA/SwissFEL_CAV/soc.srcs/sources_1/ipshared/psi.ch/version_date_v1_0/abf1293a/hdl/version_date_v1_0_user.vhd:149]
WARNING: [Synth 8-3848] Net slv_reg_rd[28] in module/entity version_date_v1_0_user does not have driver. [c:/temp/G/GPAC/Board/GPAC3_0/SYS_FPGA/SwissFEL_CAV/soc.srcs/sources_1/ipshared/psi.ch/version_date_v1_0/abf1293a/hdl/version_date_v1_0_user.vhd:149]
WARNING: [Synth 8-3848] Net slv_reg_rd[29] in module/entity version_date_v1_0_user does not have driver. [c:/temp/G/GPAC/Board/GPAC3_0/SYS_FPGA/SwissFEL_CAV/soc.srcs/sources_1/ipshared/psi.ch/version_date_v1_0/abf1293a/hdl/version_date_v1_0_user.vhd:149]
WARNING: [Synth 8-3848] Net slv_reg_rd[30] in module/entity version_date_v1_0_user does not have driver. [c:/temp/G/GPAC/Board/GPAC3_0/SYS_FPGA/SwissFEL_CAV/soc.srcs/sources_1/ipshared/psi.ch/version_date_v1_0/abf1293a/hdl/version_date_v1_0_user.vhd:149]
WARNING: [Synth 8-3848] Net slv_reg_rd[31] in module/entity version_date_v1_0_user does not have driver. [c:/temp/G/GPAC/Board/GPAC3_0/SYS_FPGA/SwissFEL_CAV/soc.srcs/sources_1/ipshared/psi.ch/version_date_v1_0/abf1293a/hdl/version_date_v1_0_user.vhd:149]
INFO: [Synth 8-256] done synthesizing module 'version_date_v1_0_user' (129#1) [c:/temp/G/GPAC/Board/GPAC3_0/SYS_FPGA/SwissFEL_CAV/soc.srcs/sources_1/ipshared/psi.ch/version_date_v1_0/abf1293a/hdl/version_date_v1_0_user.vhd:103]
INFO: [Synth 8-256] done synthesizing module 'version_date_v1_0' (130#1) [c:/temp/G/GPAC/Board/GPAC3_0/SYS_FPGA/SwissFEL_CAV/soc.srcs/sources_1/ipshared/psi.ch/version_date_v1_0/abf1293a/hdl/version_date_v1_0.vhd:103]
INFO: [Synth 8-256] done synthesizing module 'soc_version_date_inst_0' (131#1) [c:/temp/G/GPAC/Board/GPAC3_0/SYS_FPGA/SwissFEL_CAV/soc.srcs/sources_1/bd/soc/ip/soc_version_date_inst_0/synth/soc_version_date_inst_0.vhd:98]
INFO: [Synth 8-256] done synthesizing module 'soc' (132#1) [C:/temp/G/GPAC/Board/GPAC3_0/SYS_FPGA/SwissFEL_CAV/soc.srcs/sources_1/bd/soc/hdl/soc.vhd:2157]
INFO: [Synth 8-256] done synthesizing module 'soc_wrapper' (133#1) [C:/temp/G/GPAC/Board/GPAC3_0/SYS_FPGA/SwissFEL_CAV/soc.srcs/sources_1/bd/soc/hdl/soc_wrapper.vhd:24]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:01:41 ; elapsed = 00:01:46 . Memory (MB): peak = 596.316 ; gain = 423.203
---------------------------------------------------------------------------------

...

 

By the way, I copied the script directly into the Vivado "Tcl Console" and it updates the constants as it should. So it appears as if the tcl code itself is ok but needs to be called by Vivado... but how?

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Teacher muzaffer
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Registered: ‎03-31-2012

Re: Vivado ELABORATE_PROC

>> source C:/temp/G/GPAC/Board/GPAC3_0/SYS_FPGA/SwissFEL_CAV/date_generate.tcl

>> I do not see this script ever being called in the synthesis log.

 

I am not sure what you expect to happen. Your script gets called as shown in the first line. In the code you have shown there is only a proc in the script. So running it only defines the proc. You actually have to call the proc. In the tcl file add a call to the proc after the last curly brace of the proc.

 

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Explorer
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Registered: ‎01-09-2012

Re: Vivado ELABORATE_PROC

Hello Victorious (muzaffer)

 

Sure, the call of the tcl function has to be at the end... in the mean time I think I have almost solved the riddle:

Needed is something like:

 

proc date_generate {} {

   add_files C:/Work/projects/Vivado/soc.srcs/sources/bd/soc/soc.bd
   open_bd_design {C:\Work\projects\Vivado\soc.srcs\sources\bd\soc\soc.bd}

   puts "Compilation date and time is set to:"

   set date_raw     [clock seconds]
   set cell_handle [get_bd_cells {version_date_inst}]

   set c_date [clock format $date_raw -format %Y]
   scan $c_date "%d" c_date_int
   set_property CONFIG.C_DATE_YEAR [expr $c_date_int] $cell_handle
   puts "C_DATE_YEAR   : $c_date_int"

   set c_date [clock format $date_raw -format %m]
   scan $c_date "%d" c_date_int
   set_property CONFIG.C_DATE_MONTH [expr $c_date_int] $cell_handle
   puts "C_DATE_MONTH  : $c_date_int"

   set c_date [clock format $date_raw -format %e]
   scan $c_date "%d" c_date_int
   set_property CONFIG.C_DATE_DAY [expr $c_date_int] $cell_handle
   puts "C_DATE_DAY    : $c_date_int"

   set c_date [clock format $date_raw -format %k]
   scan $c_date "%d" c_date_int
   set_property CONFIG.C_DATE_HOUR [expr $c_date_int] $cell_handle
   puts "C_DATE_HOUR   : $c_date_int"

   set c_date [clock format $date_raw -format %M]
   scan $c_date "%d" c_date_int
   set_property CONFIG.C_DATE_MINUTE [expr $c_date_int] $cell_handle
   puts "C_DATE_MINUTE : $c_date_int"

   save_bd_design {C:\Work\projects\Vivado\soc.srcs\sources\bd\soc\soc.bd}
   close_bd_design [current_bd_design]

   return
}

date_generate

 

The point appears to be that I need to open the bd file make the changes, save and close it by a set of tcl commands. Ok... slowy I am approaching how the Xilinx guys want us to think.

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Explorer
Explorer
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Registered: ‎01-09-2012

Re: Vivado ELABORATE_PROC

Ok, I think this is a working possibility although not very elegant:

 

Create a user component which is connected to the axi and has generics which shall contain the synthesis date and time.

 

Capture.PNG

 

Then the date_generate.tcl script needs to be added to tcl_pre in the synthesis options.

 

proc date_generate {} {

   set path_bd [glob "../../*/*/*/*/*.bd"]
   puts "path_bd    : $path_bd"

   add_files $path_bd
   open_bd_design $path_bd

   puts "Compilation date and time is set to:"

   set date_raw     [clock seconds]
   set cell_handle [get_bd_cells {version_date_inst}]

   set c_date [clock format $date_raw -format %Y]
   scan $c_date "%d" c_date_int
   set_property CONFIG.C_DATE_YEAR [expr $c_date_int] $cell_handle
   puts "C_DATE_YEAR   : $c_date_int"

   set c_date [clock format $date_raw -format %m]
   scan $c_date "%d" c_date_int
   set_property CONFIG.C_DATE_MONTH [expr $c_date_int] $cell_handle
   puts "C_DATE_MONTH  : $c_date_int"

   set c_date [clock format $date_raw -format %e]
   scan $c_date "%d" c_date_int
   set_property CONFIG.C_DATE_DAY [expr $c_date_int] $cell_handle
   puts "C_DATE_DAY    : $c_date_int"

   set c_date [clock format $date_raw -format %k]
   scan $c_date "%d" c_date_int
   set_property CONFIG.C_DATE_HOUR [expr $c_date_int] $cell_handle
   puts "C_DATE_HOUR   : $c_date_int"

   set c_date [clock format $date_raw -format %M]
   scan $c_date "%d" c_date_int
   set_property CONFIG.C_DATE_MINUTE [expr $c_date_int] $cell_handle
   puts "C_DATE_MINUTE : $c_date_int"

   save_bd_design  [current_bd_design]
   close_bd_design [current_bd_design]

   return
}

date_generate

 

If the implementation run is completed the bd file will contain the syntesis compilation time and date.

 

      <spirit:componentInstance>
        <spirit:instanceName>version_date_inst</spirit:instanceName>
        <spirit:componentRef spirit:library="GPAC3" spirit:name="version_date" spirit:vendor="psi.ch" spirit:version="1.0"/>
        <spirit:configurableElementValues>
          <spirit:configurableElementValue spirit:referenceId="bd:xciName">soc_version_date_inst_0</spirit:configurableElementValue>
          <spirit:configurableElementValue spirit:referenceId="C_VERSION">0xbeafcace</spirit:configurableElementValue>
          <spirit:configurableElementValue spirit:referenceId="C_VERSION_MAJOR">some_project</spirit:configurableElementValue>
          <spirit:configurableElementValue spirit:referenceId="C_VERSION_MINOR">some_facility</spirit:configurableElementValue>
          <spirit:configurableElementValue spirit:referenceId="C_DATE_YEAR">2015</spirit:configurableElementValue>
          <spirit:configurableElementValue spirit:referenceId="C_DATE_MONTH">12</spirit:configurableElementValue>
          <spirit:configurableElementValue spirit:referenceId="C_DATE_DAY">8</spirit:configurableElementValue>
          <spirit:configurableElementValue spirit:referenceId="C_DATE_HOUR">11</spirit:configurableElementValue>
          <spirit:configurableElementValue spirit:referenceId="C_DATE_MINUTE">8</spirit:configurableElementValue>
        </spirit:configurableElementValues>
      </spirit:componentInstance>

 

Final comment: I think Xilinx should add a feature to the IPs which executes a tcl script at various phases of implementation... something like the tcl.pre and tcl.post inside the IP comonent. That would be more intuitive than the solution I found till now.

... There must be a more elegant way to do this.

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