03-13-2019 12:25 PM
I am seriously in trouble here. I cannot for the life of me figure out the source of these IP errors. Can anyone please provide me some things to look for regarding these errors:
[IP_Flow 19-98] Generation of IP CORE failed.
[IP_Flow 19-193] Failed to save BOM file.
I get these errors regarding multiple IPs that I had packaged that contain IP cores like BRAM controller and BRAM.
I have tried deleting the .cache folder. Deleting the offending files in the ../project.srcs/sources_1/bd/system/ip, reset the BD core's output products and regenerating them to no avail.
I have even tried recreating the IP that is instantiated into my custom IP cores... to no avail.
I have tried restarting Vivado. Restarting my machine. I have tried .ooc vs. global for the Xilinx IPs instantiated... no success.
I am using Vivado 2018.2 on a Linux Ubuntu 16.04.5 LTS. Oddly, my design did not have this problem about 3-4 weeks ago, but not that I have this issue, it refuses to be resolved. What's even more disturbing, is that I have managed a few times to somehow generate a .bit file yet it seems random!
It seems to me that the Vivado tool itself is corrupted in some way, so I am considering reinstalling it.
This has literally cost me weeks of lost productivity and is absolutely driving me mad. PLEASE, can anyone help with this issue? I have searched the forums and internet exhaustively and found little to no information on this problem.
03-14-2019 06:06 AM
Maybe this will give some insight... https://forums.xilinx.com/t5/Installation-and-Licensing/IP-Flow-19-98-Generation-of-the-IP-CORE-failed/m-p/824066#M20594
Hope that Helps
If so, Please mark as solution accepted. Kudos also welcomed. :-)
03-14-2019 07:20 AM
I don't know how the link you posted has anything to do with my issue as the IP cores I am using are included with my Xilinx license. Recall also, that sometimes I can run successfully. I don't see how my issue could be related to licensing?
An example, I somehow ran a successful build yesterday after running the tcl command "reset_project" and this worked! Yet now this morning same error AGAIN: [IP_Flow 19-993] Could not find IP file for IP 'div_32div25', which is a Xilinx Divider IP. Note, I have seen this error with block rams and controllers too.
03-14-2019 09:56 AM
Hi @cleigeber ,
Can you provide the vivado.log which will show all the critical warnings errors to evaluate?
03-14-2019 12:33 PM
Just finished a build. The problem is that it happens then I am fighting it for several days. Lately, running the tcl clean_project, reset BD output products, regenerate BD output products, and then running implementation seems to help. Without doing these steps, I believe the errors still occur. I will check once I have this next build completed- I will try rerunning it with no changes made to the source files and see what happens.
Right now, I cannot give you the requested log as it was cleared and is currently running now.
Thank you for the responses!
03-14-2019 12:58 PM
The other oddity is that one of my IP cores constantly results in "IP Catalog is out-of-date" without any underlying changes to the source files. No matter how many times I select, "Refresh IP Catalog" followed by upgrading the IP in the IP Status, once a build is kicked off it flags for needing updated again. It is an endless loop it seems...
03-14-2019 01:57 PM
I do not see a vivado.log file. There was an old one, but none corresponding to my current builds and tools. I do see log files in the synthesis and implementation folders.
03-14-2019 02:38 PM
Short status as I continue to troubleshoot this issue. It appears this IP catalog out-of-date issue may be the culprit because:
1. When I run reset_project and then run the build it completes fine.
2. When I run "Refresh IP Catalog" and then upgrade IP, the build fails synthesis almost immediately. Note also that the "IP Catalog is out-of-date" comes immediately back as well.
I am thinking that I must rebuild a completely new IP for that one module and see if it clears up this issue. Something is corrupted or invalid in the IP catalog or something.
03-18-2019 07:34 AM
Are you sure that Vivado 2018.2 even produces a vivado.log file? I have searched my project folder, there is no vivado.log file.
03-18-2019 10:07 AM - edited 03-18-2019 10:11 AM
Hi @cleigeber ,
Can you rebuild a new project from scratch and try to add an Xilinx IP and check? If it errors out can you post all the critical warnings and errors which tool shows ?
If it still errors out then have a look into this thread - https://forums.xilinx.com/t5/Synthesis/Vivado-2018-3-fails-OOC-synthesis-of-Memory-Block-Generator-8-4/m-p/951010#M30373
It may help you out.