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Observer
Observer
14,669 Views
Registered: ‎07-03-2012

Vivado IP integrator custom peripheral

Hi,

How to add a custom peripheral to the ip integrator?

Marcin

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Xilinx Employee
Xilinx Employee
14,664 Views
Registered: ‎08-02-2011

By using the IP Packager tool

www.xilinx.com
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Observer
Observer
14,642 Views
Registered: ‎07-03-2012

Is it possible to automatically migrate an XPS peripheral to the IP Integrator, I'm thinking of axi_ipif in particular?

I've done it manually with IP packager adding all hdl dependent files, but it's a bit of work.

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Xilinx Employee
Xilinx Employee
14,637 Views
Registered: ‎08-02-2011

Yes, there is actually. I believe there is a flow where you can basically point to a pcore and it will bring that in as an IP for you. But I have not done this myself yet, so I can't offer too much advice :) Check the doc for info or maybe someone else can help.

www.xilinx.com
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Xilinx Employee
Xilinx Employee
14,527 Views
Registered: ‎08-21-2007

Check out page 49 of UG896 (v2013.1) - Converting Legacy EDK IP to IP Integrator Cores
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Visitor
Visitor
14,420 Views
Registered: ‎06-04-2013

Hi,

    I am also working with custom peripheral in Vivado 2013.1. I used the custom peripheral source files from my Planhead project in IP package and intefaced the IP (simple register) with processing system in Vivado GUI. I am debugging it in Logic analyzer and successful in writes but not the raeds. Anoying thing is processing system do not asserts ARVALID which is zero all the time. 

Need your feedback and possible suggestions.

Thanks in advance.

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Observer
Observer
14,398 Views
Registered: ‎07-03-2012

Hi,

not sure if it's related but check out the register:

LVL_SHFTR_EN   @   0xF8000900

 

If you boot the PS without configuring the PL automatically and then configure PL through the cable the PS-PL axi bus accesses will hang the processor. You need to write 0xf to the above register to make it work, but if the PL is configured automatically during boot the register is already set by PS.

Marcin

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Visitor
Visitor
14,392 Views
Registered: ‎06-04-2013

Hi Marcin,

Thanks for your reply. I am not using Windows 7 and reading and writing data via SDK. 

I followed the zedboard exmaple of creating cutom peripheral (simple register)  XPS.

In vivado I used those custome peripheral source file to create an IP using IP Package.

I instatiated that IP in Vivado GUI and connected that with M_AXI_GPO port of processign system block. Valiodated the design, synthesized, implemented and generated the bitstream. I imported the HW to SDk and using mread_reg and mwrite_reg functions to  read and write from custom peripheral IP.

Address of  custom peripheral register id 0x43C00000 (64K).

Writes are successful with proper handshaking between master nad salve in all the three AXI write channels.

But for read master (processing system ) is not asserting the AXI_ARVALID???

I hope now you will be able to understand my peoblem.

I am attaching the Vivado GUI snapshot herewith. 

 

Vivado GUI setup.png
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Scholar
Scholar
13,831 Views
Registered: ‎09-05-2011

Hi,

 

Please check the following AR:

http://www.xilinx.com/support/answers/56358.htm

 

Regards,

Highlighted
11,103 Views
Registered: ‎02-07-2008

I've written a walk through for creating custom IP in Vivado here:

 

Creating a custom IP block in Vivado

 

I've shared the source code on Github here:

 

https://github.com/fpgadeveloper/microzed-custom-ip