10-04-2013 12:16 PM
I have added an IP design to the Vivado IP catalog. I have then used it in a design. I have made some modifications to the IP source files. So how do I get Vivado to update the IP in the catalog to use the new files?
10-04-2013 05:43 PM - edited 10-04-2013 06:57 PM
I tried a simple design with small changes in the top level after pacaking and noticed that you need to repackage it inorder to have the changes applied.
Also I believe it depends on the hierarchy of the source files that you were actually trying to modify.
Will investigate more and get back to you.
10-05-2013 01:00 AM
I did some changes to the source files and also added another FIFO using from the IP catalog. I then did the package IP but it didn't seem to update the changes. In EDK in the MPD file, you could add a development instruction
OPTION ARCH_SUPPORT_MAP = (others=DEVELOPMENT)
which would force the tool to rescan the IP. Maybe something similar is possible in Vivado?
10-05-2013 08:45 PM
Did you add the created IP to IP repository and then generated this new IP core?
Are there any warnings/errors during packaging of IP?
Refer to http://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_2/ug939-vivado-designing-with-ip-tutorial.pdf for help on how to package the IP.
10-07-2013 05:20 AM
I originally created a Vivado project that I then packaged as an IP. I then created another project. This project uses a Zynq so I created a block diagram. I did the Add IP to place my IP into the block diagram and wired it up. I then updated the IP in the first project (removed some ports and added some VHDL). I then repackaged the IP. Then I went back to the block diagram. But the IP is the old version. The ports that I removed are still there. So how do I get Vivado to use the new IP?
10-07-2013 05:23 AM - edited 10-07-2013 05:30 AM
Did you replace IP in block diagram with new version of pacakged IP? Try to delete/remove the old core and then add the newly packaged core to the bd.
10-07-2013 08:32 AM
I believe there is no defined flow for changing the source files after packaaging the IP and infact needs to be investigated.
Can you please package your modified files(which include FIFO) from the scratch and see if the changes are getting updated.
10-07-2013 10:49 AM
The solution seems to be that after repackaging the IP, you then need to remove the old files in the project where the IP is used. So I selected the block diagram file in the project manager view, then right clicked and selected "Reset Output Products". This then removed the old files. Then when you start the synthesis it copies the new files that it requires into the project.
10-24-2013 12:06 AM
Do I need replace the IP manually every time I repacked it? This approach is slightly awkward and error-prone keeping in mind I have to reconnect all the wires manually. There is Report IP status item in the Tool menu which can provide me with IP current & recommended versions, so as I understand there should be a way to update the IP core (at least when the interface rest the same).
I created and packaged IP core. Then I created new project, added the IP into repository and placed it in block diagram.
Then I made some changes in IP, repackaged it in other zip-file and add this zip-file into the repository. So in Repository Manager I can see two IPs in the repository, those two changes in version only. Nevertheless IP status reports that IP is up-to-date and current version equals recommended one (both are old version). I tried to regenerate output products but it made no difference.
So how can I tell Vivado that new version of the IP is available and I wish to update it? I believe it's possible.