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Participant seyyedi
Participant
4,509 Views
Registered: ‎01-05-2015

Vivado - Network Address Confilict [BD 41-1377]

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Hi all,

 

in vivado, when I instantiate 2 microblaze plus a processing system I get the following critical message:

 

 [BD 41-1377] Network address <0x00000000 [ 512M ]> is occupied by different peripherals, </microblaze_1_local_memory/dlmb_bram_if_cntlr/SLMB/Mem> in </microblaze_1/Data> and by </processing_system7_0/S_AXI_GP0/GP0_DDR_LOWOCM> in </microblaze_0/Data>. This is illegal and must be resolved before passing validation

 

Why I get this message? and how can I resolve it?

 

Thanks

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Moderator
Moderator
8,244 Views
Registered: ‎09-12-2007

Re: Vivado - Network Address Confilict [BD 41-1377]

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This is because the microblaze bram is at 0x0 and so is the ps OCM. In my design the instruction AXI wasn't enabled so I didn't see this issue.

If you want to use this topology, you can change the bram address and update the microblaze config to update the boot vector to reflect this change

View solution in original post

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Participant seyyedi
Participant
4,501 Views
Registered: ‎01-05-2015

Re: Vivado - Network Address Confilict [BD 41-1377]

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Even with a processing system and a microblaze with both data and cache memory, I get the following:

 

 [BD 41-1377] Network address <0x00000000 [ 512M ]> is occupied by different peripherals, </microblaze_0_local_memory/ilmb_bram_if_cntlr/SLMB/Mem> in </microblaze_0/Instruction> and by </processing_system7_0/S_AXI_GP0/GP0_DDR_LOWOCM> in </microblaze_0/Data>. This is illegal and must be resolved before passing validation.

 

P.S. I need to have S_AXI_GP0 enabled on the processing system in my design.

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Participant seyyedi
Participant
4,498 Views
Registered: ‎01-05-2015

Re: Vivado - Network Address Confilict [BD 41-1377]

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Here is a snapshot of the Address Editor:

address.png

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Moderator
Moderator
8,245 Views
Registered: ‎09-12-2007

Re: Vivado - Network Address Confilict [BD 41-1377]

Jump to solution
This is because the microblaze bram is at 0x0 and so is the ps OCM. In my design the instruction AXI wasn't enabled so I didn't see this issue.

If you want to use this topology, you can change the bram address and update the microblaze config to update the boot vector to reflect this change

View solution in original post