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Explorer
Explorer
1,103 Views
Registered: ‎12-07-2018

Vivado Newbie: Help adding SystemVerilog File as a module to the block design

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Hello, I'm new to Vivado and like using the Block Design using modules from my RTL. I have created a project with a Block Design and created a single SystemVerilog file. When I try to add in the file as a module it won't let me. If I choose "Show incompatible modules" from the Add Modules window I do see my module but I don't know why I can't add it to the Block design.

Add_Module.jpgI will also upload my  project. Is SystemVerilog files not allowed?

 

Thanks,

Joe

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1 Solution

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Moderator
Moderator
1,042 Views
Registered: ‎03-16-2017

Re: Vivado Newbie: Help adding SystemVerilog File as a module to the block design

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Hi @joe306,

As per latest UG 994, SV module reference in BD is not supported.  (See below are the limitations of the module ref. feature)

moduleref.JPG

you can only use verilog and VHDL to use the "add module" functionality.

 To integrate your IP in a BD, you can try to instantiate it in a verilog file and then add this verilog file as a module.

 

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
11 Replies
Scholar watari
Scholar
1,100 Views
Registered: ‎06-16-2013

Re: Vivado Newbie: Help adding SystemVerilog File as a module to the block design

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Hi @joe306

 

I confirmed your system verilog file.

Because of this file has a mistake in line 36. So, Vivado can not add this module.

 

Would you make sure it ?

 

Best regards,

 

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Explorer
Explorer
1,099 Views
Registered: ‎12-07-2018

Re: Vivado Newbie: Help adding SystemVerilog File as a module to the block design

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I tried with a file that has a Verilog extension and as able to add it to the Block Design, so my guess it that SystemVerilog is only allowed for Simulation.

Comments?

 

Joe

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Explorer
Explorer
1,089 Views
Registered: ‎12-07-2018

Re: Vivado Newbie: Help adding SystemVerilog File as a module to the block design

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I changed the file to

 


module flip_bit(
    input logic clockin,
    input logic resetin,
    input logic [31:0] data_in,
    output logic [15:0] data_out
    );
    

endmodule

 

And still could not add it to the Block Design. Can you try?

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Explorer
Explorer
1,066 Views
Registered: ‎12-07-2018

Re: Vivado Newbie: Help adding SystemVerilog File as a module to the block design

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Anyone know if you can and SystemVerilog RTL as a module to a Block Design?

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Moderator
Moderator
1,043 Views
Registered: ‎03-16-2017

Re: Vivado Newbie: Help adding SystemVerilog File as a module to the block design

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Hi @joe306,

As per latest UG 994, SV module reference in BD is not supported.  (See below are the limitations of the module ref. feature)

moduleref.JPG

you can only use verilog and VHDL to use the "add module" functionality.

 To integrate your IP in a BD, you can try to instantiate it in a verilog file and then add this verilog file as a module.

 

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
Explorer
Explorer
1,025 Views
Registered: ‎12-07-2018

Re: Vivado Newbie: Help adding SystemVerilog File as a module to the block design

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Hello, thanks for responding to my post. Do you know if Xilinx has plans to fix this in the future?

Explorer
Explorer
1,017 Views
Registered: ‎12-07-2018

Re: Vivado Newbie: Help adding SystemVerilog File as a module to the block design

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Hello, one more question. Can you recommend any documentation that will help me learn how to package the SystemVerilog File as an IP and then import the IP to the block diagram?

 

Thanks,

Joe

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Moderator
Moderator
1,009 Views
Registered: ‎03-16-2017

Re: Vivado Newbie: Help adding SystemVerilog File as a module to the block design

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Hi @joe306,

 

Have a look in UG 994, 896.

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
Explorer
Explorer
1,007 Views
Registered: ‎12-07-2018

Re: Vivado Newbie: Help adding SystemVerilog File as a module to the block design

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Thank you

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787 Views
Registered: ‎02-10-2019

Re: Vivado Newbie: Help adding SystemVerilog File as a module to the block design

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I'm facing the same issue. Would wrapping the SV module under a verilog module work? Has anyone tried it? Thanks.
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755 Views
Registered: ‎02-10-2019

Re: Vivado Newbie: Help adding SystemVerilog File as a module to the block design

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Answering my own question here, yes, I can wrap SV in verilog to use in the block design. 

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