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Visitor markus-zzz
Visitor
1,341 Views
Registered: ‎03-23-2018

Vivado PS without GUI mode

I am trying to find a way to use the processor system (PS) inside my Zedboard FPGA without using the Vivado GUI. So far I have the following trivial example working in Vivado TCL mode.

 

$ vivado -mode tcl -source compile.tcl

 

with compile.tcl containing:

-------------------------------------

create_project -in_memory -part xc7z020clg484-1
read_verilog top_top.v
synth_design -top top_top -part xc7z020clg484-1

opt_design

set_property PACKAGE_PIN T22 [get_ports {LEDG[0]}]
set_property IOSTANDARD "LVCMOS33" [get_ports {LEDG[*]}]

place_design
phys_opt_design
route_design

set_property BITSTREAM.STARTUP.STARTUPCLK JtagClk [current_design]
set_property BITSTREAM.CONFIG.DCIUPDATEMODE Quiet [current_design]
write_bitstream -verbose -mask_file -force top.bit

exit

 

Now what I would like to do is to simply instantiate an instance of 'processing_system7' inside my top_top.v but when I try to do that the synthesizer complains that the module is unknown. Is there no way that I can simply instantiate it inside top_top.v? Alternatively can it be done with few lines in the compile.tcl script?

 

 

 

 

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8 Replies
Voyager
Voyager
1,319 Views
Registered: ‎06-20-2017

Re: Vivado PS without GUI mode

I'm assuming you want to do non-project batch flow.

 

You could generate the IP like other IP you want to instantiate.  Turn it into a core container (e.g., from a managed IP project) and use the instantiation template and include the .xcix file with

 

read_ip [glob xcix/CLKWIZ145.xcix xcix/CLKWIZ100.xcix xcix/processing_system7_0.xcix]

 

I haven't played around a ton because I like IPI, but here are some helpful hints that worked for me to get IP to be used in a non-project batch flow.  Hopefully this will help you as you engineer your way through this problem:

1.  Synthesize through elaboration, then read the ip, then do a full synthesis

 

read_verilog ...
read_vhdl ...
read_xdc ...
synth design -rtl -top ... ;# elaborate without IP
read_ip [glob xcix/CLKWIZ100.xcix xcix/processing_system7_0.xcix]; #reaad the IP
synth_design -top ...;# note this is the second synth, but first full synth
...

 

Note, in your instantiations of your IP for elaboration, you may need to add the black_box attribute:

 

 

(* black_box *) module CLKWIZ100(...); // see UG901

I'm not sure if there is a more elegant way with non-project batch flow, but this worked for me using other IP and core containers.  It took me awhile to figure out so I hope you find it useful.

 

I have not tried it with the PS because I like that IPI helps me avoid structural coding.  I suppose I could turn a whole BD into a piece of IP by packing it, and then using the packaged block diagram.

 

You'll have to struggle through creating a .hdf file, but look through UG835 and its reference to get something to export to SDK.

 

 

Adaptable Processing coming to an IP address near you.
Scholar pedro_uno
Scholar
1,318 Views
Registered: ‎02-12-2013

Re: Vivado PS without GUI mode

This topic has come up before.  The consensus is that the best way to get to a working design is to use the IP Integrator block diagram editor.  If you really want to get IPI out of your flow, the recommendation was to use IPI to make a design and then save the generated HDL as source.

 

In my case, I just decided to use IPI for all processor or PCIe work.

 

Good luck.

----------------------------------------
DSP in hardware and software
-----------------------------------------
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Scholar jmcclusk
Scholar
1,310 Views
Registered: ‎02-24-2014

Re: Vivado PS without GUI mode

It can be done, but it's a moderately complex process...   Here's an example from Analog Devices Github repo:

 

https://github.com/analogdevicesinc/hdl/blob/master/projects/common/zed/zed_system_bd.tcl

 

 

Don't forget to close a thread when possible by accepting a post as a solution.
Scholar hbucher
Scholar
1,303 Views
Registered: ‎03-22-2016

Re: Vivado PS without GUI mode

@markus-zzz What about this

 

 # constants
set origin_dir "/home/hbucher"
set proj_name "project_6"
set proj_board "digilentinc.com:zybo:part0:1.0"
set proj_part "xc7z010clg400-1"

# create project
create_project $proj_name $origin_dir/$proj_name -part $proj_part
set_property board_part $proj_board [current_project]
set_property target_language VHDL [current_project]

# Create design
create_bd_design "design_1"
update_compile_order -fileset sources_1

# Add PS, apply defaults
create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0
apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {make_external "FIXED_IO, DDR" apply_board_preset "1" Master "Disable" Slave "Disable" } [get_bd_cells processing_system7_0]

# Create GPIO and add buttons and switches
create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0
apply_board_connection -board_interface "btns_4bits" -ip_intf "axi_gpio_0/GPIO" -diagram "design_1"
apply_board_connection -board_interface "sws_4bits" -ip_intf "axi_gpio_0/GPIO2" -diagram "design_1"
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {Master "/processing_system7_0/M_AXI_GP0" intc_ip "New AXI Interconnect" Clk_xbar "Auto" Clk_master "Auto" Clk_slave "Auto" } [get_bd_intf_pins axi_gpio_0/S_AXI]

# Create another GPIO and add leds
create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_1
apply_board_connection -board_interface "leds_4bits" -ip_intf "axi_gpio_1/GPIO" -diagram "design_1"
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {Master "/processing_system7_0/M_AXI_GP0" intc_ip "/ps7_0_axi_periph" Clk_xbar "Auto" Clk_master "Auto" Clk_slave "Auto" } [get_bd_intf_pins axi_gpio_1/S_AXI]

# Make wrapper
validate_bd_design
make_wrapper -files [get_files $origin_dir/$proj_name/$proj_name.srcs/sources_1/bd/design_1/design_1.bd] -top
add_files -norecurse $origin_dir/$proj_name/$proj_name.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.vhd

# Add your sources
add_files ...
add_files ...

# Make bitstream
launch_runs impl_1 -to_step write_bitstream -jobs 4

 

Then once the basic project is in place, you can add your verilog sources and integrate  with the rest of the project.  

vitorian.com --- We do this for fun. Always give kudos. Accept as solution if your question was answered.
I will not answer to personal messages - use the forums instead.
Visitor markus-zzz
Visitor
1,222 Views
Registered: ‎03-23-2018

Re: Vivado PS without GUI mode

First of all thanks for all the replies.

 

I think that the last suggestion by @hbucher is closest to what I want to achive so slightly modified that leaves me with the following script.

 

# constants
set origin_dir $::env(PWD)
set proj_name "ps-gpio-test"
set proj_board "em.avnet.com:zed:part0:1.3"
set proj_part  "xc7z020clg484-1"

# create project
create_project $proj_name $origin_dir/$proj_name -part $proj_part
set_property board_part $proj_board [current_project]
set_property target_language verilog [current_project]

# Create IP core
create_peripheral user.org user myip2 1.0 -dir $origin_dir/ip_repo
add_peripheral_interface S00_AXI -interface_mode slave -axi_type lite [ipx::find_open_core user.org:user:myip2:1.0]
generate_peripheral [ipx::find_open_core user.org:user:myip2:1.0]
write_peripheral [ipx::find_open_core user.org:user:myip2:1.0]
set_property ip_repo_paths $origin_dir/ip_repo/myip2_1.0 [current_project]
update_ip_catalog -rebuild

# Create design
create_bd_design "design_1"
update_compile_order -fileset sources_1

# Add PS, apply defaults
create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0
apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {make_external "FIXED_IO, DDR" apply_board_preset "1" Master "Disable" Slave "Disable" } [get_bd_cells processing_system7_0]

# Add IP core
create_bd_cell -type ip -vlnv user.org:user:myip2:1.0 axi_myip_0
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {Master "/processing_system7_0/M_AXI_GP0" intc_ip "New AXI Interconnect" Clk_xbar "Auto" Clk_master "Auto" Clk_slave "Auto" } [get_bd_intf_pins axi_myip_0/S00_AXI]

# Make wrapper
validate_bd_design
make_wrapper -files [get_files $origin_dir/$proj_name/$proj_name.srcs/sources_1/bd/design_1/design_1.bd] -top
add_files -norecurse $origin_dir/$proj_name/$proj_name.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v

# Add your sources
#add_files ...
#add_files ...

# Make bitstream
launch_runs impl_1 -to_step write_bitstream -jobs 4
wait_on_run impl_1

exit

Now the main reason that I want to avoid the GUI and creating projects in the GUI is that I want to minimize the amount of files that I have to push to version control. This approach does seem to achive that.

 

However when the IP core (myip2) is created as above it does produce two files 

./ip_repo/myip2_1.0/hdl/myip2_v1_0_S00_AXI.v
./ip_repo/myip2_1.0/hdl/myip2_v1_0.v

that seem to get automatically included. The design I am working on i.e. the actual intended contents of the IP core reside elsewhere so I do need to link them in somehow and also my design already has an AXI slave controller so I want to replace the one in myip2_v1_0_S00_AXI.v with my own. How should I do that? Or is there any way to have the tools not generate it in the first place?

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Voyager
Voyager
1,191 Views
Registered: ‎06-20-2017

Re: Vivado PS without GUI mode

Take a look at write_bd_tcl and/or write_project_tcl.  These will generate tcl scripts to recreate your project, and reduce the number of files you need to check into revision control.

Adaptable Processing coming to an IP address near you.
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Scholar markcurry
Scholar
1,185 Views
Registered: ‎09-16-2009

Re: Vivado PS without GUI mode

 

We solve this the same way we solved it for the Virtex4 Pro - after all the PS is nothing more than a hard core just like the PPC440s were.  We just created a wrapper for the PS, then only exposed those ports of the PS that we desired to use.  All else were tied off / no-connected.

 

So, the PL logic is controlled ( just as it always was ) by pure RTL design.  The hardmacro PS, is, well a hard macro - nothing to configure there.  The normal: read RTL, apply constraints, build flow still works for us.

 

Now the $#@$@#$! flow to generate the PS HDF files and other ancillary stuff in order to boot the PS, that's another (painful) story: https://forums.xilinx.com/t5/Vivado-TCL-Community/export-hwdef-sysdef-for-FSBL-and-devicetree-WITHOUT-USING-ANY/td-p/794843

 

 

But the PL, builds just like any other FPGA for us.

 

Regards,

 

Mark

Scholar hbucher
Scholar
1,173 Views
Registered: ‎03-22-2016

Re: Vivado PS without GUI mode

@markus-zzz You can perhaps do this

 

set obj [get_filesets sources_1]
set_property "ip_repo_paths" "[file normalize "$origin_dir/../../ip/repository"]" $obj
update_ip_catalog
vitorian.com --- We do this for fun. Always give kudos. Accept as solution if your question was answered.
I will not answer to personal messages - use the forums instead.