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Explorer
Explorer
8,844 Views
Registered: ‎12-06-2013

Vivado clocking wizard diagram port renaming bug

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Vivado 2015.2

Win7, SP1

Clocking Wizard v5.1

 

Openned the clocking wizard and tried to rename the ports as per the latest PG065 and the names are grayed out, i.e. I can't name the ports. 

portRenaming.png

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Explorer
Explorer
15,913 Views
Registered: ‎12-06-2013

Re: Vivado clocking wizard diagram port renaming bug

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The effort to fix this would be minimal but yes, this query has been adequately addressed. Thanks all!

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8 Replies
Xilinx Employee
Xilinx Employee
8,790 Views
Registered: ‎10-24-2013

Re: Vivado clocking wizard diagram port renaming bug

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Hi @jeff_king,

 

I see no issues editing the port names at my end. Attaching the screenshot. Can you please show us the other tabs also?

Thanks,Vijay
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Xilinx Employee
Xilinx Employee
8,781 Views
Registered: ‎02-06-2013

Re: Vivado clocking wizard diagram port renaming bug

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Hi

 

If you are using the clocking wizard in IPI then you cannot rename the ports in the GUI.

 

The renaming is available only in RTL projects.

Regards,

Satish

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Xilinx Employee
Xilinx Employee
8,775 Views
Registered: ‎02-14-2014

Re: Vivado clocking wizard diagram port renaming bug

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Hello @jeff_king,

 

This issue is already reported to our development team through change request and since the Clocking Wizard is not allowing the user to modify the port name, having port renaming tab is of no use. So it is decided to remove this tab (when using Clocking wizard in IPI) in Clocking WIzard (5.2) which will be incorporated in Vivado 2015.3. You can only see this tab when you are not using IPI.

Regards,
Ashish
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Explorer
Explorer
8,674 Views
Registered: ‎12-06-2013

Re: Vivado clocking wizard diagram port renaming bug

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@ashishd

 

This would still be a nice feature, so close, why not just make it work? With the amount of time Xilinx has put into making block diagrams like actual schematics I would think that fixing this would be the only diligent solution.

 

Regards,

 

-JK

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Xilinx Employee
Xilinx Employee
8,664 Views
Registered: ‎10-24-2013

Re: Vivado clocking wizard diagram port renaming bug

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Hi @jeff_king

This is by design. In a normal IP the user has to write HDL. In the IPI flow the tool generates the HDL for the user and the port names mean something to IPI and hence the user is not allowed to change them.

 

This is the reason behing disabling this in the latest version.

Thanks,Vijay
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Teacher muzaffer
Teacher
8,645 Views
Registered: ‎03-31-2012

Re: Vivado clocking wizard diagram port renaming bug

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>> With the amount of time Xilinx has put into making block diagrams like actual schematics I would think that fixing this would be the only diligent solution

in a schematic system, one can name the nets but the port names are usually fixed unless one changes the symbol. I guess Xilinx is saying that the user doesn't get to edit the symbol of the clock wizard.
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Xilinx Employee
Xilinx Employee
8,578 Views
Registered: ‎10-24-2013

Re: Vivado clocking wizard diagram port renaming bug

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Hi @jeff_king

 

Did that answer your query? If yes, please close the thread by marking the solution in the interest of other users.

 

Thanks,Vijay
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Explorer
Explorer
15,914 Views
Registered: ‎12-06-2013

Re: Vivado clocking wizard diagram port renaming bug

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The effort to fix this would be minimal but yes, this query has been adequately addressed. Thanks all!

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