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mikezgrt
Observer
Observer
2,263 Views
Registered: ‎03-05-2014

Vivado could not automatically find derived clock

Vivado will not create clocks or generated clocks as I specify in my .xdc.  Very confused as to what is going on.  Im using Vivado 15.4.  

 

So my design is super simple, its our IP core which has 4 clock domains.  I am bringing in a master clock (System_clock) to a PLL (this PLL resides outside my core) and then I generate the four clocks and connect them to the core clock inputs.  I want vivado to recognize the output clocks as the name I give it in my .xdc (thus the create_generated_clock directive), but there are several problems. 

 

1)  Vivado will simply not recognize the PLL outputs per the port names, it attaches the IP name to the port name

  • so instead of clk_out1, its clk_out_CDC_PLL

2)  When i create_generated_clocks to assign a clock to the PLL outputs, vivado still does not accept those names.

  • when I run clock interaction tool, it still has the four clocks as the pin names on the PLL.

 

Here is my XDC snippet:

 

create_clock -period 10.000 [get_ports System_clk]    -- Input clock
set_property IOSTANDARD LVCMOS25 [get_ports System_clk]
set_property PACKAGE_PIN K28 [get_ports System_clk]

create_generated_clock -name tx_pixel_clk [get_pins CDC_Clocks/clk_out1_CDC_PLL]

create_generated_clock -name rx_pixel_clk [get_pins CDC_Clocks/clk_out2_CDC_PLL]

create_generated_clock -name TX_word32_clk [get_pins CDC_Clocks/clk_out3_CDC_PLL]

create_generated_clock -name RX_word32_clk [get_pins CDC_Clocks/clk_out4_CDC_PLL]

 

Here is my PLL component and instantiation:

 

component CDC_PLL
port
(-- Clock in ports
clk_in1 : in std_logic;
-- Clock out ports
clk_out1 : out std_logic;
clk_out2 : out std_logic;
clk_out3 : out std_logic;
clk_out4 : out std_logic;
-- Status and control signals
reset : in std_logic;
locked : out std_logic
);
end component;

 

 

====Instantiation=====

CDC_Clocks : CDC_PLL
port map (

-- Clock in ports
clk_in1 => System_clock,
-- Clock out ports
clk_out1 => tx_pixel_clk,
clk_out2 => rx_pixel_clk,
clk_out3 => TX_word32_clk,
clk_out4 => RX_word32_clk,
-- Status and control signals
reset => System_reset,
locked => open
);

 

 

So....

Why does the output pin on the PLL map to:

CDC_Clocks/clk_out1_CDC_PLL

instead of:

CDC_Clocks/clk_out1

 

Why does Vivado STILL not map my -name XXXXX to the PLL output clock? 

 

Thanks for the help, I hope this is understandable.

 

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4 Replies
avrumw
Expert
Expert
2,246 Views
Registered: ‎01-23-2009

If you are going to rename the automatically generated clocks using the create_generated_clock command, I am pretty sure the object specified in the command must match (exactly) the object to which the original automatically generated clocks are attached.

 

The automatically generated clocks are attached to the output pins of the PLL - you can see this if you do report_clocks on your design (without the clock renaming).

 

Your create_generated_clocks appear to be using the output pins of the instance of the entity that instantiates the PLL. These pins are not the same pins as where the automatically generated clocks were attached...

 

You will need to dig down one level of hierarchy further to get to the actual pins of the PLL (PLLE2_BASE or PLLE2_ADV).

 

Avrum

mikezgrt
Observer
Observer
2,227 Views
Registered: ‎03-05-2014

Thanks for the Reply Avrum,  Here is my report_clocks output followed by my .xdc adjustments.  Can you make a recommendation as to how to tweak?  I'd really like the clocks renamed for CDC analysis that we will be using to present for customers.  Also find the attached image of my CDC report that I really need the clocks renamed.

 


Clock Report


Attributes
P: Propagated
G: Generated
V: Virtual
I: Inverted

Clock Period(ns) Waveform(ns) Attributes Sources
System_clock 10.000 {0.000 5.000} P {System_clock}
clkfbout_CDC_PLL 40.000 {0.000 20.000} P,G {CDC_Clocks/inst/plle2_adv_inst/CLKFBOUT}
clk_out1_CDC_PLL 9.412 {0.000 4.706} P,G {CDC_Clocks/inst/plle2_adv_inst/CLKOUT0}
clk_out2_CDC_PLL 9.412 {0.000 4.706} P,G {CDC_Clocks/inst/plle2_adv_inst/CLKOUT1}
clk_out3_CDC_PLL 6.275 {0.000 3.137} P,G {CDC_Clocks/inst/plle2_adv_inst/CLKOUT2}
clk_out4_CDC_PLL 6.275 {0.000 3.137} P,G {CDC_Clocks/inst/plle2_adv_inst/CLKOUT3}


====================================================
Generated Clocks
====================================================

Generated Clock : clkfbout_CDC_PLL
Master Source : CDC_Clocks/inst/plle2_adv_inst/CLKIN1
Master Clock : System_clock
Edges : {1 2 3}
Edge Shifts(ns) : {0.000 15.000 30.000}
Generated Sources : {CDC_Clocks/inst/plle2_adv_inst/CLKFBOUT}

Generated Clock : clk_out1_CDC_PLL
Master Source : CDC_Clocks/inst/plle2_adv_inst/CLKIN1
Master Clock : System_clock
Edges : {1 2 3}
Edge Shifts(ns) : {0.000 -0.294 -0.588}
Generated Sources : {CDC_Clocks/inst/plle2_adv_inst/CLKOUT0}

Generated Clock : clk_out2_CDC_PLL
Master Source : CDC_Clocks/inst/plle2_adv_inst/CLKIN1
Master Clock : System_clock
Edges : {1 2 3}
Edge Shifts(ns) : {0.000 -0.294 -0.588}
Generated Sources : {CDC_Clocks/inst/plle2_adv_inst/CLKOUT1}

Generated Clock : clk_out3_CDC_PLL
Master Source : CDC_Clocks/inst/plle2_adv_inst/CLKIN1
Master Clock : System_clock
Edges : {1 2 3}
Edge Shifts(ns) : {0.000 -1.863 -3.725}
Generated Sources : {CDC_Clocks/inst/plle2_adv_inst/CLKOUT2}

Generated Clock : clk_out4_CDC_PLL
Master Source : CDC_Clocks/inst/plle2_adv_inst/CLKIN1
Master Clock : System_clock
Edges : {1 2 3}
Edge Shifts(ns) : {0.000 -1.863 -3.725}
Generated Sources : {CDC_Clocks/inst/plle2_adv_inst/CLKOUT3}

 

 

======.xdc adjustments (still not working) ==================

create_clock -period 10.000 -name System_clk -waveform {0.000 5.000} [get_ports System_clk]
set_property IOSTANDARD LVCMOS25 [get_ports System_clk]
set_property PACKAGE_PIN K28 [get_ports System_clk]


create_generated_clock -name tx_pixel_clk [get_pins {CDC_Clocks/inst/plle2_adv_inst/CLKOUT0}]
#
create_generated_clock -name rx_pixel_clk [get_pins {CDC_Clocks/inst/plle2_adv_inst/CLKOUT1}]
#
create_generated_clock -name TX_word32_clk [get_pins {CDC_Clocks/inst/plle2_adv_inst/CLKOUT2}]
#
create_generated_clock -name RX_word32_clk [get_pins {CDC_Clocks/inst/plle2_adv_inst/CLKOUT3}]

 

CDC.JPG

 

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chrisz
Xilinx Employee
Xilinx Employee
2,198 Views
Registered: ‎05-06-2008

I recommend upgrading to Vivado 2018.2. The constraints you have listed based upon the report_clocks look fine, which means that we may have fixed something between 2015.4 and 2018.2.
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graces
Moderator
Moderator
2,094 Views
Registered: ‎07-16-2008

Is this a top level .xdc? I observe the port clock name doesn't match.

 

Clock Report

System_clock 10.000 {0.000 5.000} P {System_clock}

 

.xdc

create_clock -period 10.000 -name System_clk -waveform {0.000 5.000} [get_ports System_clk]
set_property IOSTANDARD LVCMOS25 [get_ports System_clk]
set_property PACKAGE_PIN K28 [get_ports System_clk]

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