Vivado critical warning when creating hardware wrapper

[gmortimer@ferrari.it]

Hi there

I am constructing a zedboard system using Vivado 2017.1. I have a Zynq Processing System block connected to a single AXI peripheral, and have used the design assistant to add the DDR and Fixed IO interfaces. When I add a hardware wrapper to this design, I get two critical warnings:

[PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.009 . PS DDR interfaces might fail when entering negative DQS skew values.

[PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.061 . PS DDR interfaces might fail when entering negative DQS skew values.

Can these warnings be ignored?

Best regards

Geoff 

[muzaffer]

gmortimer@ferrari.it are these numbers you entered manually? If so, there is some chance that they'll cause issues. I have never seen any warnings like this.

[gmortimer@ferrari.it]

No nothing entered manually, just used automatic tools. I know DDR2 is timing-critical, horrible stuff, but these numbers came from Vivado. I am using 17.1 (lovely improvements) but no manual intervention. I can send you the project if you like.

Best regards Muzaffer,

Geoff

[peteralieber]

I ran into this exact issue. I am simply following the very basic getting started tutorial with a processing system and GPIO. All is automated, and using 2017.1

[powarznybiznesmen]

Exactly same values on my side, I was also following a guide

[baxter2002]

Same thing here with a Zedbaord project imported to vivado 2017.1 from vivado 20116.4:

There were CRITICAL WARNINGS during the implementation:
CRITICAL WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.009 . PS DDR interfaces might fail when entering negative DQS skew values.
CRITICAL WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.061 . PS DDR interfaces might fail when entering negative DQS skew values.
CRITICAL WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.009 . PS DDR interfaces might fail when entering negative DQS skew values.
CRITICAL WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.061 . PS DDR interfaces might fail when entering negative DQS skew values.
CRITICAL WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.009 . PS DDR interfaces might fail when entering negative DQS skew values.
CRITICAL WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.061 . PS DDR interfaces might fail when entering negative DQS skew values.
CRITICAL WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.009 . PS DDR interfaces might fail when entering negative DQS skew values.
CRITICAL WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.061 . PS DDR interfaces might fail when entering negative DQS skew values.
CRITICAL WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.009 . PS DDR interfaces might fail when entering negative DQS skew values.
CRITICAL WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.061 . PS DDR interfaces might fail when entering negative DQS skew values.

[songmh]

Well，I have the exactly same warning. It is solved by changing the two values to positive. 

[mattyj207]

Same issue here. Different base board. Upgrading from previous version of Vivado. It did not give me this error previously. I think Vivado must be handling something differently in the presets of the boards. I haven't tried running it yet on the hardware with this warning.

[jeffrey.johnson]

Same experience here. I would like to add that this is an intermittent problem, because I've seen that the same script will sometimes pass without any critical warning.

Checking the parameter values using get_property has shown me that the values are always negative, regardless of whether the critical warning appeared or not. Same values too if you do the same thing in Vivado 2016.4 (or earlier) and use this command to check one of the parameter values:

get_property CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 [get_bd_cells processing_system7_0]

You see that the parameter is the same negative number, but Vivado 2016.4 and earlier versions didn't complain about it.

So I think it's safe to ignore this critical warning. Setting the values to positive numbers might actually create a problem with the DDR interface, so I don't think that's a viable solution.

Jeff

[mikro_wang]

the same issue. I am following one tutorial from Zynq Book for Zed/Zybo board.

My vivado is 2017.1

The examples in the tutorials could be done successfully besides this kind of warning.

[jeffrey.johnson]

Hi,

I just tested this in Vivado 2017.2 and the critical warnings still occur.

Jeff

[lbyoopp]

Hi, the same problem on me using Microzed with default board definition file, no manual intervention.

[PSU-1] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.073 . PS DDR interfaces might fail when entering negative DQS skew values. 
[PSU-2] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.072 . PS DDR interfaces might fail when entering negative DQS skew values. 

[hbucher]

@lbyoopp gmortimer@ferrari.it @jeffrey.johnson @mikro_wang @mattyj207

Quick update here. 

I got exactly the same messages (exact same numbers) when building a Zybo project with Vivado HLS. 

On vivado I had set to the Zybo board - latest release - and on HLS I set the part to xc7z010clg400-1

I was testing my top function with several interfaces and these messages only appeared when I created one m_axi interface and connected it on my Vivado design to the PS HP slave port.

The only way to get it solved was to delete my HLS component, delete all the AXI interconnects and resets then add them again from the catalog.

Then the messages magically disappeared. WTH no idea.

[mattyj207]

Just an update from my earlier post:

I can confirm that I am able to run my updated 2017.1 project successfully in Hardware after receiving these warnings.

I haven't seen any new issues in the hardware between the old project (2015.2) and the updated project (2017.1).

Right now I'm operating under the assumption that it is OK to ignore the warning.

[bigbrett]

Can confirm, just got this message using the 2017.2 toolsuite, when adding a simple HLS AXI4-lite slave block to the PS in block designer. 

Does anyone know if Xilinx is aware of this yet? 

[ziladdev]

Same here. Vivado 2017.2 a simple design with PS7 and a uart lite just testing a hello world application. One thing i noticed is that if I re-run the validate design:

 tcl_console:

validate_bd_design
CRITICAL WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.009 . PS DDR interfaces might fail when entering negative DQS skew values. 
CRITICAL WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.061 . PS DDR interfaces might fail when entering negative DQS skew values. 
validate_bd_design -force

No critical warnings on the second pass of validate design. All seem to work fine.

[prashbor]

I also came across this warning message when I validated my design for the first time. I just rerun the validate and the warning message went off. Try to rerun the validation. If you have found some other solution let us know.  

[olebon01]

Using Vivado 2017.3 with MIcrozed and the messages are still there:

[PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.073 . PS DDR interfaces might fail when entering negative DQS skew values.

[PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.072 . PS DDR interfaces might fail when entering negative DQS skew values.

Is this really a risk?

[tcachat@metraware.com]

With Vivado 2017.4, a Zynq7 Processing System and a DDR that is known from Vivado (and automatically configured) I have about the same critical warning:

[PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.017 . PS DDR interfaces might fail when entering negative DQS skew values.

It seems that when I uncheck the "Internal Vref" in the DDR Configuration, the warning disappears.

You can also look at

https://forums.xilinx.com/t5/Design-Entry/2017-2-PSU-1-critical-warning-with-basic-Zynq-design-on-DDR/m-p/789339/highlight/true#M14285

According to it, one should not worry...

[dylan]

Correct, this is a warning that updated PCB guidelines UG933 do not allow negative DQS. I've seen issues with LPDDR2 memories with negative values, which changing to a slightly positive value resolve.

For DDR3 and the Zedboard, I do not expect any issues, based on how the training algorithm operates. With all of the automatic training enabled by default for DDR3, these values are only initial starting points.

Perhaps it would make sense for Avnet/Xilinx to change these values to +.001ns to reduce confusion or use Vivado message suppression to avoid it. I've created a CR to request these.

I've also filed A CR to address the strange behavior that disabling Internal Vref suppresses the warning- there is no reason for that to occur.

[mark.harfouche]

Seems like this issue is still persisting.

I think one can go into the board file and go to preset.xml and set:

        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0" value="0.001"/>
        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1" value="0.001"/> 

at the appropriate location

[arkay99]

It is still persisting here... 2018.2. It also affected my board. Zybo Z7-20. The board would pass timing and when I invoked the SDK to work on C code the system would DL the bitstream, set up like it was ready to hit my breakpoint (early in main) and then nothing. When I changed the values to all zeros (just spitballing) the project worked again... i.e. I could step, breakpoints got hit, variables and registers had valid data, etc. Now I'm also wondering about the 4 DQ[xx:xx] values

[ronnywebers]

@dylan, I just came accross this same issue - you wrote : 

"Perhaps it would make sense for Avnet/Xilinx to change these values to +.001ns to reduce confusion or use Vivado message suppression to avoid it. I've created CR-993325 to request these."

Do you have any update on this? I tried searching for CR-993325, but not sure if we as forum members can see these?

[bernardojvm]

I had the same problem when I change from a zc706 board to a zedboard, my solution was to create all the block diagram again,  only updating blocks the final result gave problems.