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Explorer
Explorer
11,038 Views
Registered: ‎08-18-2011

Vivado deletes one pin of a differential clock in from XDC

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Vivado 2014.1/2 on Win7 and SLED11

 

Where I have the following in my XDC:

 

set_property PACKAGE_PIN AC8 [get_ports REFCLK_100M_N]
set_property PACKAGE_PIN AC9 [get_ports REFCLK_100M_P]

 

after some time I look at the file and one of the pair has been deleted to show, e.g.:

 

set_property PACKAGE_PIN AC9 [get_ports REFCLK_100M_P]

 

The project still builds and works and I haven't been able to catch Vivado in the act.

 

 

 

Does anyone else notice this?

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Explorer
Explorer
18,891 Views
Registered: ‎08-18-2011

I always run right though from synthesis to bitstream.

 

Now that I know the behaviour, I can work around it.

 

Whilst it doesn't necessarily break anything, It's quite frustrating when Vivado decides to edit my files, much like when planahead would break up my constraints into multiple lines.

View solution in original post

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5 Replies
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Scholar
Scholar
11,035 Views
Registered: ‎11-21-2013

Yes, this is "normal", i.e. whenever there is an LVDS I/O, be it clock or gp, defining one pin is enough, the other is picked automatically. This has been the same with the ISE.

Vladislav Muravin
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Xilinx Employee
Xilinx Employee
11,030 Views
Registered: ‎02-16-2014

Hi,

 

As Vlad mentioned, whenever differential I/O standard is used defining the property for one pin is enough.

Even though that constraint was removed it will be fixed to corresponding diffrential pin, you can check in I/O planning view opening the implemented design.

 

Untitled.png

 

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Explorer
Explorer
11,025 Views
Registered: ‎08-18-2011

The issue is that Vivado deletes one of the lines from my source file - even if that is the pin of the pair I have chosen to attach the constraint to

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Moderator
Moderator
11,014 Views
Registered: ‎07-16-2008

Did you perform some I/O planning operations in synthesized design and then save the design?

It's possible that the tool re-organize the package pin constraining in the saved XDC.

However, removing the N side port placement should allow implementation to complete and does no harm to the design.

 

If you see some other constraints are removed unexpectedly, that needs to be investigated.

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Highlighted
Explorer
Explorer
18,892 Views
Registered: ‎08-18-2011

I always run right though from synthesis to bitstream.

 

Now that I know the behaviour, I can work around it.

 

Whilst it doesn't necessarily break anything, It's quite frustrating when Vivado decides to edit my files, much like when planahead would break up my constraints into multiple lines.

View solution in original post

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