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Observer
Observer
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Registered: ‎11-19-2017

Vivado encrypted code causes error while implementing

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I get IEEE 1735 v2 encryption license for Vivado 2018.3 and it works with Xsim simulation,

but it causes error with synthesis. Any solutions?

 

[Vivado project error]

...

INFO: [Common 17-83] Releasing license: Synthesis

362 Infos, 275 Warnings, 8 Critical Warnings and 0 Errors encountered.

synth_design completed successfully

synth_design: Time (s): cpu = 00:00:50 ; elapsed = 00:00:52 . Memory (MB): peak = 2425.617 ; gain = 1054.207 ; free physical = 236 ; free virtual = 42566

# write_edif -force -security_mode all ${module}.edn

ERROR: [Designutils 20-2284] Design protected by IEEE 1735 V2  may not be written to EDIF

INFO: [Common 17-206] Exiting Vivado at Sat May 11 11:51:10 2019...

 

[Error from license server]

...

11:39:19 (xilinxd) OUT: "EncryptedWriter_v2" adki@AndoUbuntu  

11:39:19 (xilinxd) IN: "EncryptedWriter_v2" adki@AndoUbuntu  

11:42:15 (xilinxd) UNSUPPORTED: "Internal_bitstream" (PORT_AT_HOST_PLUS   ) adki@AndoUbuntu  (No such feature exists. (-5,346))

11:42:15 (xilinxd) UNSUPPORTED: "Internal_bitstream" (PORT_AT_HOST_PLUS   ) adki@AndoUbuntu  (No such feature exists. (-5,346))

 

For your information, I used following settings.

[Key-File]

`pragma protect version = 2

`pragma protect encrypt_agent = "XILINX"

`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2017"

`pragma protect begin_commonblock

`pragma protect control error_handling = "delegated"

`pragma protect control decryption=(activity==simulation) ? "true" : "true"

`pragma protect end_commonblock

`pragma protect begin_toolblock

`pragma protect rights_digest_method="sha256"

`pragma protect key_keyowner = "Xilinx", key_keyname= "xilinxt_2017_05", key_method = "rsa", key_public_key

MIIBIjANBgkqhkiG9w0BAQEFAAOCAQ8AMIIBCgKCAQEAxngMPQrDv/s/Rz/ED4Ri

j3tGzeObw/Topab4sl+WDRl/up6SWpAfcgdqb2jvLontfkiQS2xnGoq/Ye0JJEp2

h0NYydCB5GtcEBEe+2n5YJxgiHJ5fGaPguuM6pMX2GcBfKpp3dg8hA/KVTGwvX6a

L4ThrFgEyCSRe2zVd4DpayOre1LZlFVO8X207BNIJD29reTGSFzj5fbVsHSyRpPl

kmOpFQiXMjqOtYFAwI9LyVEJpfx2B6GxwA+5zrGC/ZptmaTTj1a3Z815q1GUZu1A

dpBK2uY9B4wXer6M8yKeqGX0uxDAOW1zh7tvzBysCJoWkZD39OJJWaoaddvhq6HU

MwIDAQAB

`pragma protect control xilinx_configuration_visible = "true"

`pragma protect control xilinx_enable_modification = "true"

`pragma protect control xilinx_enable_probing = "true"

`pragma protect control xilinx_enable_netlist_export = "true"

`pragma protect control xilinx_enable_bitstream = "true"

`pragma protect control decryption=(xilinx_activity==simulation) ? "true" : "true"

`pragma protect end_toolblock = ""

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Moderator
Moderator
619 Views
Registered: ‎09-15-2016

Re: Vivado encrypted code causes error while implementing

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Hi @andoki ,

>> 

INFO: [Common 17-83] Releasing license: Synthesis

362 Infos, 275 Warnings, 8 Critical Warnings and 0 Errors encountered.

synth_design completed successfully

synth_design: Time (s): cpu = 00:00:50 ; elapsed = 00:00:52 . Memory (MB): peak = 2425.617 ; gain = 1054.207 ; free physical = 236 ; free virtual = 42566

# write_edif -force -security_mode all ${module}.edn

ERROR: [Designutils 20-2284] Design protected by IEEE 1735 V2  may not be written to EDIF

INFO: [Common 17-206] Exiting Vivado at Sat May 11 11:51:10 2019...

 

-- Are you trying to write netlist (EDIF) of the encrypted source file? If yes, then i dont think it is possible to use write_edif for writing netlist. Please use write_verilog or write_vhdl to write the netlist for encrypted sources.

Please refer the below posts :

https://forums.xilinx.com/t5/Design-Entry/Encrypting-netlist-as-edn-in-Vivado/td-p/868675

https://forums.xilinx.com/t5/Design-Tools-Others/IEEE1735-encryption-and-EDIF/td-p/762851 

 

Thanks & Regards,
Sravanthi B
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Moderator
Moderator
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Registered: ‎09-15-2016

Re: Vivado encrypted code causes error while implementing

Jump to solution

Hi @andoki ,

>> 

INFO: [Common 17-83] Releasing license: Synthesis

362 Infos, 275 Warnings, 8 Critical Warnings and 0 Errors encountered.

synth_design completed successfully

synth_design: Time (s): cpu = 00:00:50 ; elapsed = 00:00:52 . Memory (MB): peak = 2425.617 ; gain = 1054.207 ; free physical = 236 ; free virtual = 42566

# write_edif -force -security_mode all ${module}.edn

ERROR: [Designutils 20-2284] Design protected by IEEE 1735 V2  may not be written to EDIF

INFO: [Common 17-206] Exiting Vivado at Sat May 11 11:51:10 2019...

 

-- Are you trying to write netlist (EDIF) of the encrypted source file? If yes, then i dont think it is possible to use write_edif for writing netlist. Please use write_verilog or write_vhdl to write the netlist for encrypted sources.

Please refer the below posts :

https://forums.xilinx.com/t5/Design-Entry/Encrypting-netlist-as-edn-in-Vivado/td-p/868675

https://forums.xilinx.com/t5/Design-Tools-Others/IEEE1735-encryption-and-EDIF/td-p/762851 

 

Thanks & Regards,
Sravanthi B
----------------------------------------------------------------------------------------------
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Give Kudos to a post which you think is helpful and reply oriented.
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