cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Visitor
Visitor
10,310 Views
Registered: ‎03-24-2015

Vivado generate verilog module when custom ip

Hi friend,

 

Previously we use ISE to generate ip and we can get verilog file. 

 

Now we want to use vivado to speed up the implementation. But after customing IP, the module file type is VHDL. We are not familiar to VHDL, it there any method to generate verilog module from vivado?

 

Thanks,

 

0 Kudos
4 Replies
Highlighted
Xilinx Employee
Xilinx Employee
10,304 Views
Registered: ‎02-16-2014

Hi,

 

In the project settings check what is the target language has been set to?

If it has been set to VHDL try changing it to verilog and generate the output products for IP again.

By default vivado will gnearte the top level IP products according to the project target language.

 

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
10,303 Views
Registered: ‎02-06-2013

Hi

 

If you set the target language as VHDL the top level file will be generated in VHDL but still the lower level files will be generated in vhdl or verilog depending on how the core is coded.

 

Which IP are you generating and seeing this issue.

 

Can you paste a snapshot of it.

Regards,

Satish

--------------------------------------------------​--------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful.
--------------------------------------------------​-------------------------------------------
0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
10,292 Views
Registered: ‎02-14-2014

Hello,

Please check this AR
http://www.xilinx.com/support/answers/51041.html
Regards,
Ashish
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
0 Kudos
Highlighted
Visitor
Visitor
10,254 Views
Registered: ‎03-24-2015

Hi 

 

 

 

 

 

 

http://forums.xilinx.com/t5/Design-Entry/how-to-generate-blk-ram-ip-within-verilog-in-vivado/m-p/336805#M3923.

 

 

 

 

cust_ip

IP_vhdl

0 Kudos