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Observer laurencebarker
Observer
1,462 Views
Registered: ‎05-27-2018

Vivado hierarchical design using blocks

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I'm a new user of Vivado 2018.1. I'm trying to design a Zynq FPGA using a series of blocks and I've been unable to find out how to use Vivado to create a hierarchical design. I've searched for and read a lot of tutorials. I don't want to hand-write Verilog; I want a block diagram based flow. I'm sure there is a simple way forward but I can't find it. I don't make a habit of asking for help but I've been staring at this for 3 days now. Sorry!

 

I expected the process to go something like this:

 

1. Design a block with say the DDS compiler IP, and other blocks

2. use behavioural simulation for that block

3. create a top level block with more IP (eg the Zynq processor system) and instantiate the block created at step 1

4. simulate the whole with behavioural simulation

… and in principle between steps 2 and 3, create other blocks that use the first one and more IP; these would then go into the top level block

 

I've been able to create the top level block (so far with only the processor subsystem in it) and a subsystem block with the DDS compiler in it. I can run a behavioural simulation on the top level block. I can't find a way to run a behavioural simulation on just the subsystem block, so I can't test it.

 

I can't then incorporate the subsystem block into the top level block. UG995 suggests that I should be able to do that (step 9, 1st paragraph page 35). If I try to add it as a module it says the block is incompatible because it is set to out-of-context synthesis. If I set synthesis on the subsystem block to global, it says "block design references are currently not enabled"

 

I have the impression that the way forward is to package my subsystem block as IP. But the likelihood is I will want to make changes to it; at this stage it will be far from complete and packaging as IP sounds like something that I should do to something near complete. I was able to package my subsystem block into IP, but I've still not been able to simulate it.

 

So my 2 questions are:

1. what is the right way to be able to run behavioural simulation on the subsystem blocks - does each have to be in its own project or is there a way to specify which one I simulate/

2. how do I incorporate a block-designed-subsystem into a higher level block?

 

If there is a tutorial or video that explains this, I apologise but I haven't found it!

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Xilinx Employee
Xilinx Employee
1,644 Views
Registered: ‎07-22-2008

Re: Vivado hierarchical design using blocks

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As of Vivado 2018.1 there is no real way for users to create and simulate hierarchical BDs.

The supported  method is, as you surmised, to package the lower level BD and then instantiate an instance of that created user IP into your higher level BD.  However, as you've seen, the packaged BD is only the generated files of the BD and does not allow you to open the BD from within your higher level BD and any change to the lower level BD will require it to be repackaged in order to be included in the other BD.  This can be a frustrating cycle if you are continuously developing both levels of BD.  If you continue this approach, I would suggest getting the BD with the DDS block as complete as possible before packaging.

 

You may want to consider using module reference for your lower level.  This will require you to learn the basics of HDL to create a module, instantiate the DDS block and any other IP blocks and hook them together.  However, as you change the connections or add IP in this HDL file you do not have to continually repackage a user IP in order to use it in a BD.

 

There are changes that will be made to an upcoming Vivado release that are intended to make hierarchical designing like you're asking about more practical than what is available at this point.

3 Replies
1,425 Views
Registered: ‎01-22-2015

Re: Vivado hierarchical design using blocks

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Hi Lawrence,

 

Welcome to the Xilinx Forum!

 

First, I must apologize - because I do not plan to answer your questions.  However, I have advice for you that I feel very strongly about.

 

       I'm a new user of Vivado 2018.1.   ….. I don't want to hand-write Verilog;

I understand from your comments that you are new to FPGA work. I discourage you from using ug995 methods as a starting point for your FPGA adventures. -and, I strongly urge you to restart your efforts by first becoming a very good HDL programmer (ie. learning Verilog or VHDL).

 

The graphical style of programming described in ug995 looks attractive – especially to newbies.  However, this style of programming is a crutch that will not support you for very long.  First, the ug995 programming style is not an industry standard like HDL and will not be portable.  Also, it won’t be long before you’ll want to look under-the-hood of the ug995 graphics – and there you will find HDL.  Finally, when things start to go wrong (eg. your project is failing timing analysis) you will need to look under-the-hood of the graphics and understand the intimate connection between HDL and the FPGA hardware to get things working properly.

 

So, please rethink how you want to start your FPGA adventures.  Consider taking some of the introductory FPGA courses offered by Xilinx and by Xilinx-authorized training centers.

 

I wish you the best,

Mark

Xilinx Employee
Xilinx Employee
1,645 Views
Registered: ‎07-22-2008

Re: Vivado hierarchical design using blocks

Jump to solution

As of Vivado 2018.1 there is no real way for users to create and simulate hierarchical BDs.

The supported  method is, as you surmised, to package the lower level BD and then instantiate an instance of that created user IP into your higher level BD.  However, as you've seen, the packaged BD is only the generated files of the BD and does not allow you to open the BD from within your higher level BD and any change to the lower level BD will require it to be repackaged in order to be included in the other BD.  This can be a frustrating cycle if you are continuously developing both levels of BD.  If you continue this approach, I would suggest getting the BD with the DDS block as complete as possible before packaging.

 

You may want to consider using module reference for your lower level.  This will require you to learn the basics of HDL to create a module, instantiate the DDS block and any other IP blocks and hook them together.  However, as you change the connections or add IP in this HDL file you do not have to continually repackage a user IP in order to use it in a BD.

 

There are changes that will be made to an upcoming Vivado release that are intended to make hierarchical designing like you're asking about more practical than what is available at this point.

Moderator
Moderator
1,298 Views
Registered: ‎06-14-2010

Re: Vivado hierarchical design using blocks

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Hello @laurencebarker,

 

This topic is still open and is waiting for you.

 

If your question is answered and/or your issue is solved, please mark a response that resolved your issue, as Accepted Solution (more info on this can be found here: https://forums.xilinx.com/t5/help/faqpage/faq-category-id/solutions#solutions). This way, the topic can be completed then. 

 

If this is not solved/answered, please reply in the thread.

 

Thanks in advance and have a great day.

Kind Regards,
Anatoli Curran,
Xilinx Technical Support
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