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Visitor dvir_berko
Visitor
10,909 Views
Registered: ‎06-23-2014

Vivado sub-core packaged in project and used in new project "Could not resolve non-primitive black box cell"

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Hi,

I have project which includes GTXs and clocking resources on vivado 2014.1.

The top level is a VHDL file which instantiates GTXs, MMCMs, BUFGs...

It has been synthesized and implemented succsessfully.

I packaged it into an IP according to UG896 and UG939.

I imported it to another TOP LEVEL project using the "IP Repository Manager".

Under "IP sources"-> "synthesis", I see all the vhdl files of the IP cores, without any exclamation mark.

The synthesise has been finished successfully.

However, the implementation failed:

[Project 1-486] Could not resolve non-primitive black box cell 'xcvr_test_top' instantiated as 'U0' ["c:/svn_proj/clarinet/comm/impl/comm_zynq.srcs/sources_1/bd/design_1/ip/design_1_xcvr_test_top_0_1/synth/design_1_xcvr_test_top_0_1.vhd":157]

where "xcvr_test_top" is the VHDL top level of the IP GTXs project, and I see the file under the sysnthesis in the "IP sources".

I tried few suggestions from xilinx forums:

1. reset the and regenerate files of the block diagram.

2. I checked that no "black_box" assigns are included

 

Thanks,

Dvir.

 

 

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Visitor dvir_berko
Visitor
16,624 Views
Registered: ‎06-23-2014

Re: Vivado sub-core packaged in project and used in new project "Could not resolve non-primitive black box cell"

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Hi Deepika,

 

I unchecked the "IsInclude" and I re-packaged the IP.

I run the synthesis again.

My design includes XILINX GTX IPs which are instantiated in a top "VHDL" file.

The sysnthesis has been finished suuccessfully, but the 2 XILINX GTX IPs were defined as black box (critical warnnings):

 

[Project 1-486] Could not resolve non-primitive black box cell 'cluster_gtx1' instantiated as 'cluster_gtx1_wrapper_1/cluster_gtx1_init_i' ["t:/vhdl/comm/impl/comm_zynq.srcs/sources_1/ipshared/elop/xcvr_test_top_v1_2/bddd9cb8/xcvr_test.srcs/sources_1/imports/support/cluster_gtx1_wrapper.vhd":504]

 

[Project 1-486] Could not resolve non-primitive black box cell 'uplink_2_5g_gtx' instantiated as 'uplink_2_5g_gtx_wrapper_1/uplink_2_5g_gtx_init_i' ["t:/vhdl/comm/impl/comm_zynq.srcs/sources_1/ipshared/elop/xcvr_test_top_v1_2/bddd9cb8/xcvr_test.srcs/sources_1/imports/support/uplink_2_5g_gtx_wrapper.vhd":419]

 

Many thanks,

Dvir

 

 

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10 Replies
Scholar muravin
Scholar
10,902 Views
Registered: ‎11-21-2013

Re: Vivado sub-core packaged in project and used in new project "Could not resolve non-primitive black box cell"

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Hey Dvir,

 

When you are saying "sub-core", do you mean "an IP in a top-level block design" or "a sub-core reference within an IP"?

 

If this is "an IP in a top-level block design", i.e. you are instantiating an IP on the top-level canvas block design, your problem is likely a missing repository path. You can examine the VDS file to see if this file is replaced by the black box during the synthesis.

 

If this is "a sub-core reference within an IP", you need to properly point the IP packager, i.e. assuming your problem *is* a sub-core reference:

1. Open your IP with the IP packager.

2. Navigate to the IP File Groups

3. In the Verilog Synthesis or VHDL Synthesis, right-clock somewhere between the RTL files and choose "Add Sub-Core Reference", then pick the library you packaged from the list of the IPs.

4. Re-package the IP.

 

Hope this helps.

Cheers Vladi

Vladislav Muravin
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Visitor dvir_berko
Visitor
10,894 Views
Registered: ‎06-23-2014

Re: Vivado sub-core packaged in project and used in new project "Could not resolve non-primitive black box cell"

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Thanks Vladi.

my design is "an IP in a top-level block design".

'xcvr_test_top' represents the sub project which I packaged into IP, and would like to use it in my main top level project. 

I checked the VDS and the "xcvr_test_top" (U0) was replaced by a black box:

.....

WARNING: [Synth 8-1090] 'xcvr_test_top' is not compiled in library xil_defaultlib [c:/svn_proj/clarinet/comm/impl/comm_zynq.srcs/sources_1/bd/design_1/ip/design_1_xcvr_test_top_0_1/synth/design_1_xcvr_test_top_0_1.vhd:57]

.....

INFO: [Synth 8-637] synthesizing blackbox instance 'U0' of component 'xcvr_test_top' [c:/svn_proj/clarinet/comm/impl/comm_zynq.srcs/sources_1/bd/design_1/ip/design_1_xcvr_test_top_0_1/synth/design_1_xcvr_test_top_0_1.vhd:157]

...

Why this file is replaced by a black box ?

 

Thanks again,

Dvir

 

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Scholar muravin
Scholar
10,888 Views
Registered: ‎11-21-2013

Re: Vivado sub-core packaged in project and used in new project "Could not resolve non-primitive black box cell"

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To be honest I never packaged projects, we only packaged directories so far. When we do that, the IP repo path is added to the main project automatically (and so it should when one packages the project). If not, we can always add the I Prepo paths manually (and I think you did).

 

The other thing is, our Verilog RTL files are normally compiled from library work and Verilog includes from xil_defaultlib. I don't know how the VHDL files are treated, but another thing you can try is go to the IP Packager -> IP File Group, and manually set the VHDL packages to be compiled from xil_defaultlib and VHDL RTL - from work.

 

Apart from that, if you try from the TCL console the following command: write_project_tcl -force [current_project].tcl, you can see the IP repo paths that the VIVADO is using. Check whether the IP repo path points to your file.

 

BR

Vlad

Vladislav Muravin
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Xilinx Employee
Xilinx Employee
10,881 Views
Registered: ‎09-20-2012

Re: Vivado sub-core packaged in project and used in new project "Could not resolve non-primitive black box cell"

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Hi @dvir_berko 

 

In most of the cases I have seen that usage of "BLACK_BOX" attribute on the IP core results in this error. But you have mentioned that there is no BLACK_BOX attribute used in your design.

 

Is it possible to share the test case so that we can have a look?

 

Thanks,

Deepika.

Thanks,
Deepika.
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Visitor dvir_berko
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Registered: ‎06-23-2014

Re: Vivado sub-core packaged in project and used in new project "Could not resolve non-primitive black box cell"

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Thanks a lot for your efforts.

There is a better way to integrate a sub-project into other main project ?

The sub-project includes 8 GTXs, MMCMs and logic.

The top level is a VHDL which instantiates all the components.

Many thanks again,

Dvir

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Visitor dvir_berko
Visitor
10,875 Views
Registered: ‎06-23-2014

Re: Vivado sub-core packaged in project and used in new project "Could not resolve non-primitive black box cell"

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Thanks Deepika.

I'll check the option to share the case and will update you soon.

There is a better way to integrate a sub-project into other main project ?

The sub-project includes 8 GTXs, MMCMs and logic.

The top level is a VHDL which instantiates all the components.

Many thanks,

Dvir

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Xilinx Employee
Xilinx Employee
10,874 Views
Registered: ‎09-20-2012

Re: Vivado sub-core packaged in project and used in new project "Could not resolve non-primitive black box cell"

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Hi Dvir,

 

Can you check if "Is_include" is checked by any chance in the IP Packager project?

 

If this is checked, uncheck it and repackage IP.

 

include_snapshot_201303140318280542.JPG

 

one related article http://www.xilinx.com/support/answers/60834.html

 

Thanks,

Deepika.

Thanks,
Deepika.
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Scholar muravin
Scholar
10,866 Views
Registered: ‎11-21-2013

Re: Vivado sub-core packaged in project and used in new project "Could not resolve non-primitive black box cell"

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Dvir,

To answer you previous question, I don't know what is "a better way" to do this. We live in a world where relativity theory plays a key role in defining the term "a better way".

 

For us, a "better way" is the one where VIVADO gives you the least problems and we had a few that slowed our migration from the XPS quite a bit (If Austin is reading this, I still don't think Xilinx is a micro squat).

 

We do have a similar project where we have proprietary Vx1 transceiver with 16 GTX lanes, along with some clocking business, and the way it worked for us is:

1. Create a top-level block design, and add IPs to it, make necessary connections, generate the HDL wrapper.

stiching al lthe IPs on it.

2. Each IP is packaged using packaging a directory (NOT PROJECT), for example, if your top-folder is $YOUR_IP_REPO_PATH/xcvr_test_top/, point the IP packager to this /xcvr_test_top folder and package it, then make all necessary interface definitions.

3. All generic primitives should be packaged as a library core and added later on as a sub-core reference.

4. Last but not least, GUI is only used for making the necessary connections between the modules; all runs are managed by TCL scripting.

 

Not sure if this is helpful to you, but this is what *worked* for us, not without some help from these forums.

 

BR

Vlad

 

Vladislav Muravin
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Visitor dvir_berko
Visitor
16,625 Views
Registered: ‎06-23-2014

Re: Vivado sub-core packaged in project and used in new project "Could not resolve non-primitive black box cell"

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Hi Deepika,

 

I unchecked the "IsInclude" and I re-packaged the IP.

I run the synthesis again.

My design includes XILINX GTX IPs which are instantiated in a top "VHDL" file.

The sysnthesis has been finished suuccessfully, but the 2 XILINX GTX IPs were defined as black box (critical warnnings):

 

[Project 1-486] Could not resolve non-primitive black box cell 'cluster_gtx1' instantiated as 'cluster_gtx1_wrapper_1/cluster_gtx1_init_i' ["t:/vhdl/comm/impl/comm_zynq.srcs/sources_1/ipshared/elop/xcvr_test_top_v1_2/bddd9cb8/xcvr_test.srcs/sources_1/imports/support/cluster_gtx1_wrapper.vhd":504]

 

[Project 1-486] Could not resolve non-primitive black box cell 'uplink_2_5g_gtx' instantiated as 'uplink_2_5g_gtx_wrapper_1/uplink_2_5g_gtx_init_i' ["t:/vhdl/comm/impl/comm_zynq.srcs/sources_1/ipshared/elop/xcvr_test_top_v1_2/bddd9cb8/xcvr_test.srcs/sources_1/imports/support/uplink_2_5g_gtx_wrapper.vhd":419]

 

Many thanks,

Dvir

 

 

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Visitor dvir_berko
Visitor
5,288 Views
Registered: ‎06-23-2014

Re: Vivado sub-core packaged in project and used in new project "Could not resolve non-primitive black box cell"

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Hi,

 

I integrated 2 different packaged IPs (VHDLs) into my block design at VIVADO.

The problem:

The synthesize reported that one of IPs was recognized as ‘black box’.

I noticed that both IPs use files from the library “proc_common_v4_0”.

However, they used different versions of the same files.

The solution:

I copied the most updated files into the older “proc_common_v4_0”.

 

Thanks for your help,

 

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