12-18-2019 03:10 PM
I generated a custom IP from a hierarchical desing (VHDL, see the picture) using Vivado's (2019.1) "Tools->Create and package new IP" function. The custom IP is used in a Microblaze block design and there were no problems implementing the IP. However, the "ADC128S102.vhd" file was changed and the changes were correctly synthesized when running synthesis on the complete IP core (top level: ADC128S102_IP_v1_0.vhd). After this, the IP was re-packaged via the "Edit packaged IP" function of Vivado.
When opening the Microblaze block design, Vivado recognizes the changes in the IP and recommends an update. The update is done, but synthesising the block design does not change the behavior of the IP (it behaves like the original version). To locate the failure, I changed the "ADC128S102_IP_v1_0_M00_AXIS.vhd", did the re-packaging and updating again and was suprised that these changes were correctly synthesized in the block diagram.
Is there something special to take care of when using a hierarchical design when creating/updating custom IP?
I also tried the "IP-XACT-File approach" for repackaging the IP , but the result was the same.
10-05-2020 12:20 PM
This post does not describe my problem. I am using Xilinx SDK 2019.1 (Eclipse) and updating the BSP has never been the problem. The problem is when I modify a custom IP (which seems to work) , repackage the IP and then update it in Vivado. Vivado puts out that the update is done successfully but synthesizing the design does not change the behavior of the custom IP (it behaves like the unmodified version).
For me it seems that there is a problem when the custom IP has a hierarchical design.
10-05-2020 02:36 PM
Indeed, this is not related to Vitis or HLS. It is strictly the IP management in Vivado block design.
By the way, I got it working after a million tries, I am not sure if a combination of my prior steps have helped but here is what I did:
1. Update your IP, package it blabla, we know how to do this.
2. Go to the.bd where your updated custom is used, right click > reset output products
3. Rerun synthesis
4. Right click the .bd from step 2 > generate output products.
5. At this point it was working in post synthesis simulation.
I am unsure if it is supposed to work that way but this seemed to have made it work for me.
Best of luck