04-24-2020 04:57 PM - edited 04-24-2020 05:02 PM
Hello, this is my first time working with FPGAs and Xilinx products, I'm currently working on a project that requires embedding a DL model on Xilinx ZC702 board working with the dpu_ip_v140. I'm running Vivado, Vitis and PetaLinux 2019.2 on Ubuntu 18.3 LTS.
So far I have imported the dpu ip in my Vivado project and created the block design and then successfully ran synthesis and implementation and generated the bitstream. Then I started following this tutorial https://github.com/JinChen-tw/pynqz2_dpu140 for the PetaLinux steps. (I'm sorry if this is too much information I just don't know what to leave out). But before advancing any further I wanted to backup my work in a git repo so I followed this tutorial http://www.fpgadeveloper.com/2014/08/version-control-for-vivado-projects.html I clicked on "File > Write project TCL" unchanged to generate the tcl script and modified it as mentioned in the tutorial, but I'm not sure which files exactly to track in the src folder, I cannot find any clear instructions or tutorial, also after pushing the tcl script and the scr folder to github I cloned the repo from github in a separate path to see if I can successfully recreate the project by sourcing the .tcl script, it seems to run without errors except for the last two lines where it tells me it cannot recreate the wrapper. Also when I run the tcl script Vivado creates another directory in the cloned project root with a new .src folder which is quite confusing.
I will attach to this post the project .tcl script for you to see the contents, as for the Vivado .gitignore contents and the files I'm backing up in github you can check them out in my github repo for the project to get an idea about the structure of my Vivado folder. If anyone could tell me which files and directories to ignore in the Vivado folder to be able to recreate the same project afterwards with the same exact tree I would really appreciate it. Sorry for the long post and thanks in advance for your help.
04-26-2020 02:10 AM
To facilitate interactions with revision control systems, you can store IP configuration files and output products in a single, binary IP core container file rather than a directory structure. The Vivado design suite interacts directly with the IP core container files. When using IP core containers, you only need to manage the IP .xcix file. The .xcix file contains all of the files required for simulation, synthesis and implementation . For more info. on using IP core containers, see UG 896, page 60 https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug896-vivado-ip.pdf
You can recreate a Vivado Design Suite design and associated IP and BD files using a set of source files. To mitigate the rist of recreation using future versions of the Vivado design suite and to reduce compile times, Xilinx recommends managing the following source files. Checking in all these files enalbes the design to be recreated using the current sources and tool configuration settings.
For more info. on Source management and Revision control recommendations , have a look into UG 949 Chapter 5:
04-27-2020 04:53 PM
Thank you for your reply, I have already read all of the UGs related to the subject and tutorials before posting this question but I can't figure out exactly what modifications should be added to the .tcl script and what files inside the .scr folder I should be tracking in order to restore my Vivado project intact in the same state, because when I source the .tcl command it creates a separate folder in the project inside th cloned git repo root folder with an additional .src folder so things get messed up and the wrapper isn't properly built. That is why I attached my .tcl script to the post and my repo git for you to see the structure.