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Newbie
Newbie
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Registered: ‎07-25-2019

Vivado without the block design

I am trying to strip the block design out of the Vivado projects I'm working on and still be able to do the Vivado to Petalinux flow. I'm using Vivado 2018.3 and Petalinux 2018.3.

If IP blocks are instantiated in a top level HDL file instead of in a block design, Vivado does not include them in the address editor / hardware handoff flow. If I edit the generated .hwh file, Petalinux won't read it in because "ERROR: [HDF 64-25] The hdf file has been tampered".

I couldn't get the AXI interconnect block to be instantiated outside of a block design, so my current project's block design is just the processing system block (for the ZC706 dev board) and an AXI interconnect. This is wrapped by the top level HDL file which also instantiates all the custom HDL blocks and Xilinx IP blocks (for example UART). Many of these blocks have AXI interfaces that will eventually be interacted with in Linux through the generic UIO driver. Since these blocks are not in the block design, they don't get put into the HDF, so they are not autogenerated into pl.dtsi.

How can I handle device tree generation if I don't want to have (much of) a block design?

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Scholar
Scholar
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Registered: ‎09-16-2009

Re: Vivado without the block design

This actually a two-part question. 

The first is how to use RTL flows only (within a MPSoC class design or not) in order to create your Programmable Logic.  There's various posts here on the forums on how to do that - even in an AXI world.  For us, we created our own set of AXI infrastructure IP using many of the higher level design constructs within SystemVerilog - interfaces (and arrays of interfaces) for AXI buses, structured configurations, and a host other tools in our toolbox. (Note we didn't have much of this when we started, one can "dip your toe in the water" and start with just a few simple infrastructure items and using just Verilog-2001.)

The second part of the question is how to use the dumb IPI/BD tooll in order to create your FSBL.  This we've NOT solved as cleanly.  Some applicable pointers are here:

https://forums.xilinx.com/t5/Vivado-TCL-Community/export-hwdef-sysdef-for-FSBL-and-devicetree-WITHOUT-USING-ANY/td-p/794843

(Sigh - I see that thread is almost two years old, and the process is still as painful today as it was then...)

The general idea - run the tool WITHOUT a PL.  You're creating a PS configuration without any PL.  The MPSoC are more like processors, in that they come up by themselves, without any need of any logic within the PL.  There's no reason to clutter this process up with PL configuration.  As I recall, you may need to create some sort of dummy PL - I think some sort of clock wrap around or something.  But this is a supported mode of operation from Xilinx.

Then configure the PS logic as desired.  Play around with export wrappers, or whatever other GUI-option-of-the-day in order to create your HDF file.  (We have to hunt and peck everytime we do this, the correct process seems to move around with every new Vivado version)

The HDF file, is a zip file. You can inspect it by unzipping.  It's integrity checked however, and none of the downstream Petalinux tools will run if you modify the HDF contents.  

Most of the HDF file is just configuration of PS Clocks, and DDR training, and a little mux selection for the PS IO.  It's in two formats, a C file that can be compiled, or a TCL file that can be directly used within the SDK.  If you create this dummy, minimal PL, there shouldn't be anything PL specific in the HDF file.  (To tell the truth, I'm not sure how/what Petalinux / the FSBL would do with a PL configuration - autoload the PL?)

Use the Petalinux tools to create the FSBL, and dts, and other related files as normal.

Boot the MPSoC, then configure the PL as you see fit - there's multiple support flows from Xilinx. Redesign the PL as you need, - you only need to do this last step again to load a new FPGA.  You don't need to muck with any of the FSBL/Petalinux stuff again.

Regards,

Mark

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