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Contributor
Contributor
9,401 Views
Registered: ‎06-09-2014

Warnings and critical warnings

Hi


How seriously do the designers here take warnings and critical warnings from Vivado?  Is it usual to plough ahead even when there are lots of warnings and critical warnings?

I've noticed going through some Vivado/SDK tutorials that there's usually lots of warnings and I get the impression most of them aren't significant.

I've now inherited a design for ZedBoard firmware and some simple test software, and Vivado gives truck-loads of warnings and critical warnings in both synthesis and implementation that the designer wasn't concerned about.

In most of the places I've worked, we've had a policy of zero warnings to avoid having significant warnings missed within an avalanche of ignored warnings.


More specificallly, some examples are:

    WARNING: [Vivado 12-584] No ports matched '[get_ports -filter { IOBANK == 13 }]'. [...]
    CRITCAL WARNING: [Common 17-55] 'set_property' expects at least one object. [...]
    WARNING: [Vivado 12-584] No ports matched 'AC_ADR0'. [...]
    CRITCAL WARNING: [Common 17-55] 'set_property' expects at least one object. [...]

which refer to the following lines from the included board XDC file:

    set_property IOSTANDARD LVCMOS33 [get_ports -filter { IOBANK == 13 } ]
    set_property PACKAGE_PIN AB1 [get_ports {AC_ADR0}]

The ports from the PACKAGE_PIN properties have the same names as pins from the ZedBoard schematic, but the only ones that are complained about are the ones that don't appear in the block design.

So, should I be creating a custom XDC that removes reference to all the ports that aren't used in the block design rather than using the standard one?

Steve

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3 Replies
Xilinx Employee
Xilinx Employee
9,395 Views
Registered: ‎09-20-2012

Re: Warnings and critical warnings

Hi Steve,

 

I would suggest you to clean up your constraints.

 

Else it may happen that there is really some issue with the design for which the tool issues Warnings/Critical Warnings and you end up ignoring or missing them.

 

Thanks,

Deepika.

Thanks,
Deepika.
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Community Manager
Community Manager
9,383 Views
Registered: ‎07-23-2012

Re: Warnings and critical warnings

Hi Steve,

The warnings during synthesis would indicate the optimizations performed on the code or if you are driving a constant to any of the pins or nets or if there are any floating nets.

The implementation tool would throw warnings for optimization of logic, logic removal, incorrect configuration of any of the primitives, unmatched constraints etc.

It is always better to have a warning free code ideally. But it is not practical.

I would recommend you to resolve the critical warnings without fail because ignoring these warning can cause adverse affects on the functionality.

In your case, you can ignore these warnings because you don't those pins in your design. But the good practice would be to define the constraints only on the used pins.

Regards,
Krishna
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Contributor
Contributor
9,368 Views
Registered: ‎06-09-2014

Re: Warnings and critical warnings

Thanks guys.  I'll try to whittle down the warnings.

 

Steve

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