08-04-2016 07:12 PM
I have a custom IP that I want to be able to send control signals to from my Zynq processor. I see that there's a CDMA IP which can connect to the Zynq to perform DMA transfers. There are also things like AXI-BRAM controllers that can connect the CDMA to a BRAM IP. What would be the best IP to use so that I can write a DMA transfer from my Zynq and end up with a standard logic vector output with whatever I wrote?
08-05-2016 01:24 AM
08-05-2016 05:53 AM
Thanks for the response, but I'm not sure if that's what I'm looking for. This seems to be a method of extracting the AXI signals from the CDMA to the upper level wrapper so it can be connected to another AXI interface on a higher level.
What I was looking for was more an AXI controller similar to the AXI BRAM Controller, but instead of converting a full AXI-4 interface to a BRAM port, it would take in an AXI-4 interface and output a direct std_logic_vector or equivalent. So if you write to the CDMA a single word of data, that data would show up on the output of the IP, which I could then connect to my other IP.
Does any IP core like that exist?
08-05-2016 09:50 AM - edited 08-05-2016 09:50 AM
The closest thing to this would be AXI DMA which gives you an AXI Stream interface (instead of AXI4 with the more advanced control signaling).
Have a look at these Zynq AXI DMA example designs to help get started:
08-11-2016 01:19 PM