What is the equivalent of processor system reset from Zynq 7000 series Soc in Virtex 7 series FPGA?
First sorry if this question is naive, for this situation, please direct me to useful links.
I am migrating a custom design from Zynq 7000 series in Ultrascale+ MPSoC to a pure fabric of Virtex-7 FPGA.
The original designs have two clock domains and two resets to the custom designs, that are realized by enabling the pl_clk0 and pl_clk1 in the processing system in the Ultrascale+ MPSoC, then the pl_reset signal is connected to two "Processor system reset" IPs together with the two clocks to generate a set of synchronous resets for bus, interconnection and peripherals.
In Virtex-7 FPGA, how could I realize such functionality?
With two clock domains and the reset synchronized with these two clock domains?
There is clock wizard which has reset input and can produce two output clock domains, Can I use then the same reset for the clock wizard, and these two output clock domains as input to two "Processor system reset" IPs?