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Scholar
Scholar
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Registered: ‎12-07-2018

When will SystemVerilog be supported in module reference in the IP Integrator Block Design?

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Hello, quick question for the forum members. I like using SystemVerilog to write my RTL code and I also like using the Block Designs. SV files are not supported in module reference within the Block Design. Are there any plans to support SV in future Vivado releases?

 

Thank you

Joe

 

 

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Moderator
Moderator
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Registered: ‎01-16-2013

Re: When will SystemVerilog be supported in module reference in the IP Integrator Block Design?

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@joe306 

 

It is in roadmap to support both System verilog and VHDL-2008 in module reference but the limitation is only when using it as a top module or entity. You can still use it by just having a Verilog wrapper around the SV file and add them to block design.

Top.v

--main.sv

https://www.xilinx.com/content/dam/xilinx/support/documentation/sw_manuals/xilinx2019_2/ug994-vivado-ip-subsystems.pdf#page=258 

 

--Syed

---------------------------------------------------------------------------------------------
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Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
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1 Reply
Highlighted
Moderator
Moderator
187 Views
Registered: ‎01-16-2013

Re: When will SystemVerilog be supported in module reference in the IP Integrator Block Design?

Jump to solution

@joe306 

 

It is in roadmap to support both System verilog and VHDL-2008 in module reference but the limitation is only when using it as a top module or entity. You can still use it by just having a Verilog wrapper around the SV file and add them to block design.

Top.v

--main.sv

https://www.xilinx.com/content/dam/xilinx/support/documentation/sw_manuals/xilinx2019_2/ug994-vivado-ip-subsystems.pdf#page=258 

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------

View solution in original post