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lalitbhambhani
Adventurer
Adventurer
11,492 Views
Registered: ‎07-23-2015

Where are the constraints files XDC

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I'm using Vivado 2015.4 with KCU105 eval board.

I'm going over the DDR4 MIG design example that is avalialbe on Xilinx's KCU105 page.  My question is regarding constraint files.

I see only 1 constraint file which has entries for LEDs on the board.

 

There are obviously other constraint files generated by the LogiCore when I generated the DDR4 IP.

If I search for *.XDC in my project directory I see many files but when I opened each one to see pin assignments, I don't see any pin location, strength, voltage level, and other constraints.

 

I did a grep recursive search for keyword "LOC" in all files with XDC extention and only the ones for the LEDs came up and not for the Address, Data, DQS, Clock, etc...where are these constraints set.

 

Thanks.

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pratham
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Registered: ‎06-05-2013

@lalitbhambhani Let me help you here to clear the confusion.

 

There are 2 things to be consider here since you are using xilinx eval board

1) If you have selected the IP interface while customizing the IP as ddr4 then vivado tool would take care of the DDR4 constraint according to your board, you need not constrain them

2) If you are not using eval board or using but while customizing MIG ip have not selected the IP interface as dd4 then tool would not apply board level constrain then user has to apply constrain by opening synthesized design (I/O pin planning).

 

Please check the attached screenshot, first one shows, you have selected ip interface which means tool would apply the constraint to mig core

Second picture shows, if you have not selected the interface, you have to assign them manually.

 

I hope this will help you.

-Pratham

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arpansur
Moderator
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Registered: ‎07-01-2015

Hi @lalitbhambhani,

 

Generally IPs will contain the clock constraints.

Please go through page-118 onwards for constraints on different components.

http://www.xilinx.com/support/documentation/boards_and_kits/kcu105/ug917-kcu105-eval-bd.pdf

You can add these constraints to .xdc according to your design requirement.

 

Thanks,
Arpan

 

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Thanks,
Arpan
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lalitbhambhani
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Registered: ‎07-23-2015

Thanks Arpan.  This atleast tells me that I can create my own constraints for the eval board I got.

But I'm still confused.  

 

I understand that the IP can create its own clock constraints.  But shouldn't that be visible to the designer.  I'm probably missing something or maybe this step should be added to the MIG example guide.I followed XTP348 to create the DDR4 MIG design example.  

 

This design example does not have all the constraints file included.  So how does Vivado know what my pin constraints are?  Does it know because I selected KCU105 board when setting up the project?

 

Thanks.

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pratham
Scholar
Scholar
19,205 Views
Registered: ‎06-05-2013

@lalitbhambhani Let me help you here to clear the confusion.

 

There are 2 things to be consider here since you are using xilinx eval board

1) If you have selected the IP interface while customizing the IP as ddr4 then vivado tool would take care of the DDR4 constraint according to your board, you need not constrain them

2) If you are not using eval board or using but while customizing MIG ip have not selected the IP interface as dd4 then tool would not apply board level constrain then user has to apply constrain by opening synthesized design (I/O pin planning).

 

Please check the attached screenshot, first one shows, you have selected ip interface which means tool would apply the constraint to mig core

Second picture shows, if you have not selected the interface, you have to assign them manually.

 

I hope this will help you.

-Pratham

----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
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vemulad
Xilinx Employee
Xilinx Employee
11,437 Views
Registered: ‎09-20-2012

Hi @lalitbhambhani

 

You can find the board pinout constraints in part0_pins.xml at <install_dir>\Xilinx\Vivado\2015.4\data\boards\board_files\kcu105\1.1

Thanks,
Deepika.
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lalitbhambhani
Adventurer
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Registered: ‎07-23-2015
@pratham, @vemulad, @arpansur

Thanks this helps a lot in understanding Vivado.

Thanks this helps a lot in understanding Vivado.
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adieux
Contributor
Contributor
2,166 Views
Registered: ‎06-19-2017

Once you selected the KCU105 board and DDR4 as the default memory, and generated the example, you will be able to Synthesis and Implement it. 

After the implemented design is open, click the Layout -> I/O planning on the top menu of Vivado. You will see the pins at the I/O ports tab at the bottom of your Vivado window. Right click on this area and select "Export", these constraints can then be exported as a .xdc file.

 

export_IO_xdc.png
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