UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Contributor
Contributor
9,579 Views
Registered: ‎07-23-2015

Where are the constraints files XDC

Jump to solution

I'm using Vivado 2015.4 with KCU105 eval board.

I'm going over the DDR4 MIG design example that is avalialbe on Xilinx's KCU105 page.  My question is regarding constraint files.

I see only 1 constraint file which has entries for LEDs on the board.

 

There are obviously other constraint files generated by the LogiCore when I generated the DDR4 IP.

If I search for *.XDC in my project directory I see many files but when I opened each one to see pin assignments, I don't see any pin location, strength, voltage level, and other constraints.

 

I did a grep recursive search for keyword "LOC" in all files with XDC extention and only the ones for the LEDs came up and not for the Address, Data, DQS, Clock, etc...where are these constraints set.

 

Thanks.

0 Kudos
1 Solution

Accepted Solutions
Scholar pratham
Scholar
17,291 Views
Registered: ‎06-05-2013

Re: Where are the constraints files XDC

Jump to solution

@lalitbhambhani Let me help you here to clear the confusion.

 

There are 2 things to be consider here since you are using xilinx eval board

1) If you have selected the IP interface while customizing the IP as ddr4 then vivado tool would take care of the DDR4 constraint according to your board, you need not constrain them

2) If you are not using eval board or using but while customizing MIG ip have not selected the IP interface as dd4 then tool would not apply board level constrain then user has to apply constrain by opening synthesized design (I/O pin planning).

 

Please check the attached screenshot, first one shows, you have selected ip interface which means tool would apply the constraint to mig core

Second picture shows, if you have not selected the interface, you have to assign them manually.

 

I hope this will help you.

-Pratham

----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
forum.JPG
forum1.JPG
6 Replies
Moderator
Moderator
9,574 Views
Registered: ‎07-01-2015

Re: Where are the constraints files XDC

Jump to solution

Hi @lalitbhambhani,

 

Generally IPs will contain the clock constraints.

Please go through page-118 onwards for constraints on different components.

http://www.xilinx.com/support/documentation/boards_and_kits/kcu105/ug917-kcu105-eval-bd.pdf

You can add these constraints to .xdc according to your design requirement.

 

Thanks,
Arpan

 

----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

Thanks,
Arpan
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
1.JPG
Contributor
Contributor
9,559 Views
Registered: ‎07-23-2015

Re: Where are the constraints files XDC

Jump to solution

Thanks Arpan.  This atleast tells me that I can create my own constraints for the eval board I got.

But I'm still confused.  

 

I understand that the IP can create its own clock constraints.  But shouldn't that be visible to the designer.  I'm probably missing something or maybe this step should be added to the MIG example guide.I followed XTP348 to create the DDR4 MIG design example.  

 

This design example does not have all the constraints file included.  So how does Vivado know what my pin constraints are?  Does it know because I selected KCU105 board when setting up the project?

 

Thanks.

0 Kudos
Scholar pratham
Scholar
17,292 Views
Registered: ‎06-05-2013

Re: Where are the constraints files XDC

Jump to solution

@lalitbhambhani Let me help you here to clear the confusion.

 

There are 2 things to be consider here since you are using xilinx eval board

1) If you have selected the IP interface while customizing the IP as ddr4 then vivado tool would take care of the DDR4 constraint according to your board, you need not constrain them

2) If you are not using eval board or using but while customizing MIG ip have not selected the IP interface as dd4 then tool would not apply board level constrain then user has to apply constrain by opening synthesized design (I/O pin planning).

 

Please check the attached screenshot, first one shows, you have selected ip interface which means tool would apply the constraint to mig core

Second picture shows, if you have not selected the interface, you have to assign them manually.

 

I hope this will help you.

-Pratham

----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
forum.JPG
forum1.JPG
Xilinx Employee
Xilinx Employee
9,524 Views
Registered: ‎09-20-2012

Re: Where are the constraints files XDC

Jump to solution

Hi @lalitbhambhani

 

You can find the board pinout constraints in part0_pins.xml at <install_dir>\Xilinx\Vivado\2015.4\data\boards\board_files\kcu105\1.1

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
Contributor
Contributor
9,338 Views
Registered: ‎07-23-2015

Re: Where are the constraints files XDC

Jump to solution
@pratham, @vemulad, @arpansur

Thanks this helps a lot in understanding Vivado.

Thanks this helps a lot in understanding Vivado.
0 Kudos
Observer adieux
Observer
253 Views
Registered: ‎06-19-2017

Re: Where are the constraints files XDC

Jump to solution

Once you selected the KCU105 board and DDR4 as the default memory, and generated the example, you will be able to Synthesis and Implement it. 

After the implemented design is open, click the Layout -> I/O planning on the top menu of Vivado. You will see the pins at the I/O ports tab at the bottom of your Vivado window. Right click on this area and select "Export", these constraints can then be exported as a .xdc file.

 

export_IO_xdc.png
0 Kudos