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Adventurer
Adventurer
2,784 Views
Registered: ‎02-09-2012

Where to find information about DDR2 cell / clock buffers?

In which document are the DDR2 cells (clock buffering to external port) decribed?

 

I did not find it amoung the buffers nor IO-docs - also CoreGen was no help.

 

Wich would be the right document to search?

 

I do not only need instantiation but also information about switching, timing etc..

 

 

 

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Instructor
Instructor
2,781 Views
Registered: ‎07-21-2009

From the New Users Forum README thread:

 

Common Interfaces and FPGA techniques:

clock forwarding to an output pin link#1  link#2

 

As for "DDR2" signal levels, specify a compatible IOSTANDARD (e.g. SSTL18_I).

 

-- Bob Elkind

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