08-17-2016 01:12 AM
Why does Vivado not create a VHDL package per IP core, which includes the component declaration of the IP core?
There are the *_stub.vhdl and *_stub.v files, but for VHDL it would be immensly helpful if I could just use a package whenever I need the IP core instead of repeatedly copying the component declaration from the *.vho file into each architecture that uses the IP. It's just annoying.
Is there a specific reason why this isn't done? Is it because no equivalence exists in Verilog and Vivado internally "prefers" Verilog?
Of course I can create the package manually and put the component declaration inside, but it's so simple yet useful, I have to ask why Vivado does not do it by default, or why it was chosen not to do so.
08-17-2016 01:29 AM