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Adventurer
Adventurer
4,386 Views
Registered: ‎02-22-2016

Why do Vivado IP cores not come with a VHDL package including the component declaration?

Why does Vivado not create a VHDL package per IP core, which includes the component declaration of the IP core?

There are the *_stub.vhdl and *_stub.v files, but for VHDL it would be immensly helpful if I could just use a package whenever I need the IP core instead of repeatedly copying the component declaration from the *.vho file into each architecture that uses the IP. It's just annoying.

Is there a specific reason why this isn't done? Is it because no equivalence exists in Verilog and Vivado internally "prefers" Verilog?

Of course I can create the package manually and put the component declaration inside, but it's so simple yet useful, I have to ask why Vivado does not do it by default, or why it was chosen not to do so.

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Xilinx Employee
Xilinx Employee
4,374 Views
Registered: ‎08-01-2008

Good Suggestions! We will report to tools R&D
Thanks and Regards
Balkrishan
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Explorer
Explorer
4,306 Views
Registered: ‎09-07-2011

You can ditch the components and use "direct" instantiation,  Components are not mandatory in VHDL, but it seems to be the de-facto style.

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