cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Turkey9999999
Observer
Observer
534 Views
Registered: ‎11-11-2020

Why is SystemVerilog "incompatiable module" for "Add module" to vivado block design?

Here's the SystemVerilog code...Why does SystemVerilog say "incompatiable module" when i right click "Add module" in vivado block design?

 

 

`timescale 1ns/10ps
 
//------------------------------------------------------------------------------------
// MODULE
//------------------------------------------------------------------------------------
module PzProgramCk #(
    parameter integer aw = 32,        
	parameter integer dw = 32,
    parameter integer iw = 12,
    parameter integer lw = 4	
) (        
     //------------------------------------------------------------------------------------
     // Verilo-2001 MACROS
     //------------------------------------------------------------------------------------

    `define xiclk(ifname, clkname, rstname, freq) \
        (* X_INTERFACE_INFO = `"xilinx.com:signal:clock:1.0 clkname CLK`" *) \
        (* X_INTERFACE_PARAMETER = `"ASSOCIATED_BUSIF ifname, ASSOCIATED_RESET rstname, FREQ_HZ freq `" *)
	
    `define xirst(rstname) \
        (* X_INTERFACE_INFO = `"xilinx.com:signal:reset:1.0 rstname RST `" *) \
        (* X_INTERFACE_PARAMETER = `"POLARITY ACTIVE_LOW`" *)

    `define xigp0(name) \
        (* X_INTERFACE_INFO = `"xilinx.com:interface:aximm:1.0 s_axi_gp0 name `" *)	

    //----------------------------------------------------------------
    // FPGA PADS
    //----------------------------------------------------------------
		
/*H6--*/output wire              fmc2_board_scl,           
/*H5--*/inout  wire              fmc2_board_sda,

   //----------------------------------------------------------------
   // Board Design Connections to ZYNQ
   //----------------------------------------------------------------
		
		`xiclk(s_axi_gp0, s_axi_gp0_aclk, s_axi_aresetn, 50000000)
        input  wire              s_axi_gp0_aclk,
		
		`xirst(clk_reset0_n)
        input  wire              s_axi_aresetn,
           
        `xigp0(ARADDR)   input  wire  [aw-1:0]     s_axi_gp0_ra_addr,           
        `xigp0(ARBURST)  input  wire  [1:0]        s_axi_gp0_ra_burst,         
        `xigp0(ARCACHE)  input  wire  [3:0]        s_axi_gp0_ra_cache,        
        `xigp0(ARID)     input  wire  [iw-1:0]     s_axi_gp0_ra_id,            
        `xigp0(ARLEN)    input  wire  [lw-1:0]     s_axi_gp0_ra_len,           
        `xigp0(ARLOCK)   input  wire  [1:0]        s_axi_gp0_ra_lock,          
        `xigp0(ARPROT)   input  wire  [2:0]        s_axi_gp0_ra_prot,          
        `xigp0(ARQOS)    input  wire  [3:0]        s_axi_gp0_ra_qos,           
        `xigp0(ARREADY)  output wire               s_axi_gp0_ra_ready,         
        `xigp0(ARSIZE)   input  wire  [2:0]        s_axi_gp0_ra_size,          
        `xigp0(ARVALID)  input  wire               s_axi_gp0_ra_valid,         
        `xigp0(AWADDR)   input  wire  [aw-1:0]     s_axi_gp0_wa_addr,          
        `xigp0(AWBURST)  input  wire  [1:0]        s_axi_gp0_wa_burst,         
        `xigp0(AWCACHE)  input  wire  [3:0]        s_axi_gp0_wa_cache,         
        `xigp0(AWID)     input  wire  [iw-1:0]     s_axi_gp0_wa_id,            
        `xigp0(AWLEN)    input  wire  [lw-1:0]     s_axi_gp0_wa_len,           
        `xigp0(AWLOCK)   input  wire  [1:0]        s_axi_gp0_wa_lock,          
        `xigp0(AWPROT)   input  wire  [2:0]        s_axi_gp0_wa_prot,          
        `xigp0(AWQOS)    input  wire  [3:0]        s_axi_gp0_wa_qos,           
        `xigp0(AWREADY)  output wire               s_axi_gp0_wa_ready,         
        `xigp0(AWSIZE)   input  wire  [2:0]        s_axi_gp0_wa_size,          
        `xigp0(AWVALID)  input  wire               s_axi_gp0_wa_valid,         
        `xigp0(BID)      output wire  [iw-1:0]     s_axi_gp0_wb_id,            
        `xigp0(BREADY)   input  wire               s_axi_gp0_wb_ready,         
        `xigp0(BRESP)    output wire  [1:0]        s_axi_gp0_wb_resp,          
        `xigp0(BVALID)   output wire               s_axi_gp0_wb_valid,         
        `xigp0(RDATA)    output wire  [dw-1:0]     s_axi_gp0_rd_data,          
        `xigp0(RID)      output wire  [iw-1:0]     s_axi_gp0_rd_id,            
        `xigp0(RLAST)    output wire               s_axi_gp0_rd_last,          
        `xigp0(RREADY)   input  wire               s_axi_gp0_rd_ready,         
        `xigp0(RRESP)    output wire  [1:0]        s_axi_gp0_rd_resp,          
        `xigp0(RVALID)   output wire               s_axi_gp0_rd_valid,         
        `xigp0(WDATA)    input  wire  [dw-1:0]     s_axi_gp0_wd_data,          
        `xigp0(WID)      input  wire  [iw-1:0]     s_axi_gp0_wd_id,            
        `xigp0(WLAST)    input  wire               s_axi_gp0_wd_last,          
        `xigp0(WREADY)   output wire               s_axi_gp0_wd_ready,         
        `xigp0(WSTRB)    input  wire  [(dw/8)-1:0] s_axi_gp0_wd_strb,          
        `xigp0(WVALID)   input  wire               s_axi_gp0_wd_valid         
);
    
endmodule

 

Tags (1)
0 Kudos
5 Replies
miker
Xilinx Employee
Xilinx Employee
527 Views
Registered: ‎11-30-2007

I think it is because you are limited to VHDL and Verilog RTL Modules (not VHDL-2008 and SystemVerilog) when using the RTL Module flow.  Please reference the Vivado Design Suite Designing IP Subsystems Using IP Integrator User Guide (UG994; v2020.1; p 249).

forums_rtl_module_support.png

Please Reply, Kudos, and Accept as Solution.
Turkey9999999
Observer
Observer
512 Views
Registered: ‎11-11-2020

Ok... thanks. didn't know that...  

0 Kudos
pavan_619@
Adventurer
Adventurer
485 Views
Registered: ‎03-13-2019

Hello @Turkey9999999 

As mentioned in UG994 currently supported languages are VHDL and verilog.


still if you want to use the system verilog codes as "add module" you can write a Verilog wrapper and use it.

0 Kudos
Turkey9999999
Observer
Observer
469 Views
Registered: ‎11-11-2020

I tried switching the file type from ".sv" to ".v" and now it works...  apparently Verilog macros argument feature was added in Verilog-2001....

0 Kudos
Turkey9999999
Observer
Observer
273 Views
Registered: ‎11-11-2020

TIP:  I found the best solution was to create verilog-2001 wrapper module that instantiates the systemverilog module, then when you "add module" the verilog-2001 module shows up in the list.   This actually works out better because it hides all the systemverilog files and just exposes the one  verilog-2001 file that you have in the design....

0 Kudos