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Observer
Observer
3,121 Views
Registered: ‎06-02-2009

XDMA Block Design set wrong MODE parameter on descriptor c2h bypass ports

Hi,

 

I am using the XDMA IP in the block designer with the descriptor bypass mode set for read (H2C) and write (C2H) DMA channels.

On the module in the block design the descriptor bypass ports are added for the channels, however the H2C descriptor bypass ports are correctly set as MASTER, but the C2H bypass descriptor ports are incorrectly set to SLAVE.

This causes an issue because on my custom RTL module which controls these ports they are both (correctly) assigned to be SLAVE interfaces, but I can't connect the C2H ports because now both modules are assigned to be slaves.

 

Is there a way to override the interface MODE setting on the C2H bypass port on the IP?

 

Thanks,

Tim

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5 Replies
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Observer
Observer
3,109 Views
Registered: ‎06-02-2009

Vivado 2017.1

 

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Observer
Observer
2,376 Views
Registered: ‎06-02-2009

Still not fixed in 2017.3 .

 

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Newbie
Newbie
2,333 Views
Registered: ‎10-30-2017

Hi tlupick,

in your VHDL source code you can define the C2H bypass interface as Master (whether it should be Master or Slave it is debatable) easily, by assigning an attribute MODE = MASTER to one of the interface signals. I discovered this by trial and error and it seems to work fine, at least at a block design level (I still have to synthesize it). For example:

 

attribute X_INTERFACE_MODE : string;
attribute X_INTERFACE_MODE of c2h_dsc_byp_ctl: signal is "MASTER";
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of c2h_dsc_byp_ctl: signal is "xilinx.com:display_xdma:dsc_bypass_rtl:1.0 my_dsc_byp_c2h dsc_byp_ctl";
attribute X_INTERFACE_INFO of c2h_dsc_byp_len: signal is "xilinx.com:display_xdma:dsc_bypass_rtl:1.0 my_dsc_byp_c2h dsc_byp_len";
attribute X_INTERFACE_INFO of c2h_dsc_byp_dst_addr: signal is "xilinx.com:display_xdma:dsc_bypass_rtl:1.0 my_dsc_byp_c2h dsc_byp_dst_addr";
attribute X_INTERFACE_INFO of c2h_dsc_byp_load: signal is "xilinx.com:display_xdma:dsc_bypass_rtl:1.0 my_dsc_byp_c2h dsc_byp_load";
attribute X_INTERFACE_INFO of c2h_dsc_byp_ready: signal is "xilinx.com:display_xdma:dsc_bypass_rtl:1.0 my_dsc_byp_c2h dsc_byp_ready";
attribute X_INTERFACE_INFO of c2h_dsc_byp_src_addr: signal is "xilinx.com:display_xdma:dsc_bypass_rtl:1.0 my_dsc_byp_c2h dsc_byp_src_addr";

 

LR

 

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1,574 Views
Registered: ‎03-22-2013

Hi,

 

In Vivado 2017.4 that seems to work well.

Tested in Verilog and VHDL.

 

ATTRIBUTE X_INTERFACE_MODE of cfg_pm_aspm_l1_entry_reject: SIGNAL IS "MASTER";

 

But in Vivado 2018.1 X_INTERFACE_MODE seems not working for verilog!

 

(* X_INTERFACE_MODE = "XIL_INTERFACENAME pcie4_cfg_pm, MASTER" *)
(* X_INTERFACE_INFO = "xilinx.com:display_pcie4:pcie4_cfg_pm:1.0 pcie4_cfg_pm pm_aspm_l1entry_reject" *)
output  wire                cfg_pm_aspm_l1_entry_reject;
(* X_INTERFACE_INFO = "xilinx.com:display_pcie4:pcie4_cfg_pm:1.0 pcie4_cfg_pm pm_aspm_tx_l0s_entry_disable" *)
output  wire                cfg_pm_aspm_tx_l0s_entry_disable;

 

Any body has an idea?

 

Best regards,

Christian

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Highlighted
1,543 Views
Registered: ‎03-22-2013

OK It seems that the correct way in verilog is

 

(* X_INTERFACE_MODE = "MASTER" *)
(* X_INTERFACE_INFO = "xilinx.com:display_pcie4:pcie4_cfg_pm:1.0 pcie4_cfg_pm pm_aspm_l1entry_reject" *)
output  wire                cfg_pm_aspm_l1_entry_reject;
(* X_INTERFACE_INFO = "xilinx.com:display_pcie4:pcie4_cfg_pm:1.0 pcie4_cfg_pm pm_aspm_tx_l0s_entry_disable" *)
output  wire                cfg_pm_aspm_tx_l0s_entry_disable;

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