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Observer kjb
Observer
10,257 Views
Registered: ‎12-03-2013

XPS project in ISE Project Navigator

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Dear Community,

 

I am having a weird problem, which I cannot find a solution in the documentation for.

 

We have an XPS design, which so far has only lived in XPS, i.e. the whole workflow has been in done using XPS and SDK alone.

 

Now I am doing a few upgrades and want to use the ISE 14.7 synthesis and simulation tools. For this I created a new Project Navigator Project and imported the system.xmp file as a source. I then generated a top HDL source from the PN menu and wanted to Export the Hardware Design to SDK with Bitstream.

 

However when I run this synthesis and Implementation finish but generating the bitstream throws an error that it cannot find a port from the UCF file in the design.

 

ConstraintSystem:59 - Constraint <NET "ADC_RESET" LOC = "V29" ;>
   [system.ucf(38)]: NET "ADC_RESET" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:Xflow - Program ngdbuild returned error code 2. Aborting flow execution...
ERROR:EDK -  
   Error while running "gmake -f system_ntfs.make init_bram".
ERROR: running XPS to load ELF data to bitstream failed.
ERROR: Bitstream data load failed, XPS did not generate /win/FPGAdev/SAMI/fpga_firmware/digitizers/xps/implementation/download.bit

 

However I can without problems export the design to SDK without a bitstream. It is very hard to find Documentation on this workflow and what I find is from ISE 11.x, which is often outdated as the new tools seem to have a lot of automation.

 

So my question is : Do I misunderstand the workflow? Is exporting to SDK without the bitstream enough, since I could program the FPGA from SDK and then use the generated download.bit in impact (which is what I have done with the XPS only workflow so far). How would I then generate the Bitstream in ISE? Older documentation was talking about updating the bitstream with the SDK elf, but I cannot find that option.

 

Just for information the ISE Project basically only contains the system.xmp and the generated top module. No other files. The UCF is in the XPS project.

 

Thanks in advance for the help.

 

PS: If I am too incompetent to google correctly and have not found the relevant documentation describing the workflow for ise 14.7 I am happy with a link.

 

 

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1 Solution

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Observer kjb
Observer
17,616 Views
Registered: ‎12-03-2013

Re: XPS project in ISE Project Navigator

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I think I found the problem in this case by accident just now.

 

As I mentioned previously the design was being used as a XPS only design before I modified it. Because I our development is happening under Linux, but the Files are stored on an NTFS drive I had to specify a custom makefile in the XPS design.  The file was based on the automatically generated one from the EDK.

 

The change made was simply running the synthesis command via bash -c "...".

 

When I moved to importing the XPS design into project navigator I did not take this out assuming that the problem would persist. Just now I removed this design file when I retried these steps as I tested it on a local linux partition(initially I had the same errors). For some reason the errors did not show up anymore and the Bitstream gets generated and exported to SDK.

 

I am guessing the project navigator makefiles are completely different from the XPS ones, which is why this now works. I didn't anticipate that..

 

I wil accept this as the solution to the problem.

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7 Replies
Observer kjb
Observer
10,253 Views
Registered: ‎12-03-2013

Re: XPS project in ISE Project Navigator

Jump to solution

So exporting without the bitstream is definitely not enough, as SDK still requires the system.bit to generate the download.bit (as I thought).

 

So the problem then runs down to why project navigator does not find the ADC_RESET port. in the design, even though it is definietly there.

 

On a side not I am surprised to receive this error in the generate Bitstream stage. Usually these errors are thrown during Map.

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Instructor
Instructor
10,235 Views
Registered: ‎08-14-2007

Re: XPS project in ISE Project Navigator

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It's possible that the ADC_RESET net has changed names as seen by ISE.  I would suggest setting the option -aul (Allow unmatched LOC constraints) for ngdbuild (translate).  That will allow the build to run through and you can then look at the pad report to see if you have any un-located pads that could account for the missing ADC_RESET.  If you find the pad with a new name, you can then change the .ucf file to use that name and run the build again.

-- Gabor
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Observer kjb
Observer
10,231 Views
Registered: ‎12-03-2013

Re: XPS project in ISE Project Navigator

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Hi there,

 

thanks for the reply.

 

So from your comment I actually changed the ISE synthesi to keep the hierarchy, just in case things got renamed. It did not solve the problem however I found the three signals in the pinout report, which is generated. (As I said the whole thing fails at the "generate bitstream" stage, which is weird in the first place).

 

So in the pinout report there are three signals that have an UNLOCATED constraint, which are ADC_RESET, REF_INT_N_EXT and AD9510_FUNCTION(Nevermind the names). These signals are special in that case that ADC_RESET, AD9510_FUNCTION are connected to NET_GND in the system.mhs file and REF_INT_N_EXT is connected to NET_VCC(They are the only signals that have that).

 

According to the pinout report they now sit at completely different pins than specified in the UCF file. It appears as though the tools do not understand the NET_GND and NET_VCC!?

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Instructor
Instructor
10,227 Views
Registered: ‎08-14-2007

Re: XPS project in ISE Project Navigator

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Unless I missed something, it sounds like these pins are tied off inside the FPGA?  i.e. what you expect is that the pins tied to NET_VCC will drive the pin high always, and those tied to NET_GND will always drive the pin low?

 

I have seen issues with some versions of ISE where such connections cause the net name to become obscured when you try to translate the design.

 

-- Gabor
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Observer kjb
Observer
10,214 Views
Registered: ‎12-03-2013

Re: XPS project in ISE Project Navigator

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That is exactly what they are supposed to do. 

 

We just want to prevent spurious stuff happening so we want well defined behaviour.

 

Since I am using the latest version of the tools I think there is some fundamental problem with the way I try to implement the design. 

 

I tried removing the above signals from the mhs file, just to see what happens, however then the tools appear to randomly remove tons of logic from my design, apparently because they are loadless signals, but I am certain that they are being used. This then leads to the bitfile not generated, because all of the logic being removed(which throws errors in the end). So the problem is not the net_vcc or net_gnd, but a fundamental problem of my workflow approach.

 

Did someone do this before, i.e. have an existing XPS design and just import it into Project Navigator to use the tools?

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Observer kjb
Observer
17,617 Views
Registered: ‎12-03-2013

Re: XPS project in ISE Project Navigator

Jump to solution

I think I found the problem in this case by accident just now.

 

As I mentioned previously the design was being used as a XPS only design before I modified it. Because I our development is happening under Linux, but the Files are stored on an NTFS drive I had to specify a custom makefile in the XPS design.  The file was based on the automatically generated one from the EDK.

 

The change made was simply running the synthesis command via bash -c "...".

 

When I moved to importing the XPS design into project navigator I did not take this out assuming that the problem would persist. Just now I removed this design file when I retried these steps as I tested it on a local linux partition(initially I had the same errors). For some reason the errors did not show up anymore and the Bitstream gets generated and exported to SDK.

 

I am guessing the project navigator makefiles are completely different from the XPS ones, which is why this now works. I didn't anticipate that..

 

I wil accept this as the solution to the problem.

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Observer kjb
Observer
8,910 Views
Registered: ‎12-03-2013

Re: XPS project in ISE Project Navigator

Jump to solution

To add to that as I just ran across this again shortly:

 

Another thing that needs to be done (additionally) is to make sure that "generate netlist" was run in xps after the system was changed! Otherwise the same error also occurs!

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