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Visitor
Visitor
6,455 Views
Registered: ‎10-16-2009

Xilinx Clocking Wizard generates poor HDL that causes useless warnings

I'm somewhat disappointed with the Xilinx Clocking Wizard...  it is creating HDL that results in useless warnings when synthesizing.

 

I have been generating single DCM cores using this wizard targetting the Spartan3A.

 

First, if you select the CLKIN source as "external", the wizard generates a useless IBUFG_OUT that causes an "output not used" synthesis warning.  This output should appear at the top schematic and allow you to uncheck a box to remove it.  I have taken to use an "Internal" source, and wiring in my own IBUFG to avoid this warning.

 

Second, when selecting a 60 Mhz clock source, the CLKIN_PERIOD is rounded to 16.667, and now I get warnings that that period does not match my 60 Mhz timing constraint.   Please do not round that value to only 3 decimals, or at least open up the tolerance on comparison to allow for it.

 

 

Darron

 

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Historian
Historian
6,450 Views
Registered: ‎02-25-2008


blacdard wrote:

I'm somewhat disappointed with the Xilinx Clocking Wizard...  it is creating HDL that results in useless warnings when synthesizing.

 

I have been generating single DCM cores using this wizard targetting the Spartan3A.

 

First, if you select the CLKIN source as "external", the wizard generates a useless IBUFG_OUT that causes an "output not used" synthesis warning.  This output should appear at the top schematic and allow you to uncheck a box to remove it.  I have taken to use an "Internal" source, and wiring in my own IBUFG to avoid this warning.

 

Second, when selecting a 60 Mhz clock source, the CLKIN_PERIOD is rounded to 16.667, and now I get warnings that that period does not match my 60 Mhz timing constraint.   Please do not round that value to only 3 decimals, or at least open up the tolerance on comparison to allow for it.

 

 

Darron

 


So, don't use the wizard.

 

Instantiating the DCM and the support components is very easy and will do what you need.

----------------------------Yes, I do this for a living.
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Highlighted
Visitor
Visitor
6,448 Views
Registered: ‎10-16-2009

Well, yeah.  It's not very hard to do that either.

 

The point is it's very mediocre quality, and easy to fix.  Stuff like this has very tangible effects on the perception of Xilinx's design software.  It's nothing like a serious issue...  but it should be fixed.

 

 

Darron

 

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Highlighted
6,376 Views
Registered: ‎10-25-2009

After you finish banging your head on the brick wall trying to get this to work, you will find that the best approach is to plan your clocking by hand, including which clock modules (dcms, plls), which gbufs and which clock pins, and then instantiate the primitives in vhdl/verilog, and add placement constraints.

For some reason, the tools have never been able to place clocks well, probably because of all the different clock placement rules. It could be that this is one of those problems that a human mind can solve much faster than a computer.

I agree that this should work better, and it is a bit of a pain to have to plan and place this yourself, but that is the state of the imperfect world we live in. Good luck.

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