02-14-2014 07:58 PM
does anybody knows the Xilinx Design Language(XDL) generated by ISE13.4?if so,please help me.
thanks in advance!
02-14-2014 08:07 PM
If you mean design entry language, Xilinx do not have separate language XDL on its own, it follows industry standard HDL (hardware description Languaage)
You can generate a design in either VHDL or Verilog, you can select the language in project options as shown below
Hope this helps.
02-14-2014 08:43 PM
If you are interested to read a XDL file after converting from NCD refer
If you would want to use Xilinx Design Language tutorial, refer
02-15-2014 04:50 AM
02-15-2014 06:19 AM
Ofcourse, type the command xdl in the command line suite as shown here.
02-15-2014 10:43 AM
@handoujack : "does anybody knows the Xilinx Design Language(XDL)"
Xilinx's original XDL documentation can be found in certain older versions of ISE/Webpack.
Download and install a copy of ISE WebPACK 6.3i from here:
Then take a look at the files in %XILINX%\help\data\xdl
02-17-2014 06:22 AM
I use the command (ISE6.3):xdl –ncd2xdl test.ncd test.xdl, and the xdl file is different from the “The Xilinx Design Language (XDL):Tutorial and Use Cases” described.
Why is my xdl file different from the file mentioned in “The Xilinx Design Language (XDL):Tutorial and Use Cases”?
07-15-2014 03:04 PM
Hi, what is the difference? Do you use the same part as they use in the tutorial? Some naming conventions seem to be different for different parts...
@brimdavis: thanks for the link to old versions - finally I have also an "official" documentation;)
01-22-2019 02:00 PM
The XDL file format has no relevance to today's FPGA designs. Why do you think you need it?
The format was barely needed in some weird design flows in the ISE days. (I don't think I ever used it outside of some PlanAhead tutorials). I don't think the file format is used in Vivado at all.
Can you give us ideas on what you're trying to accomplish?
01-24-2019 10:54 PM
Hi, I am trying to generate routing path which is a collection of subsequent PIPs and Wire segments (Interconnection resource) based on some algorithm. I want to write C code for this path generation problem which will give the output in XDL format.