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Contributor
Contributor
10,515 Views
Registered: ‎04-24-2013

Xilinx Design Language

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hi

     

      does anybody knows the Xilinx Design Language(XDL) generated by ISE13.4?if so,please help me.

 

     thanks in advance!

 

     handoujack!

 

 

   

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Xilinx Employee
Xilinx Employee
10,510 Views
Registered: ‎08-02-2007

Re: Xilinx Design Language

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Hi,

 

If you are interested to read a XDL file after converting from NCD refer 

http://www.fpgadeveloper.com/2011/06/how-to-read-an-ncd-file.html

 

If you would want to use Xilinx Design Language tutorial, refer 

http://www.mn.uio.no/ifi/english/research/projects/cosrecos/publications/paper/recosoc11beckhoff.pdf

 

http://www.ee.unlv.edu/~selvaraj/ecg707/lecture/Xilinx%20Design%20Language.pdf

 

 

--Hem

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Xilinx Employee
Xilinx Employee
10,514 Views
Registered: ‎07-11-2011

Re: Xilinx Design Language

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Hi,

 

If you mean design entry language, Xilinx do not have separate language XDL on its own, it follows industry standard HDL (hardware description Languaage)

You can generate a design in either VHDL or Verilog, you can select the language in project options as shown below

 

language.png

 

 

Hope this helps.

 

Regards,

Vanitha

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Xilinx Employee
Xilinx Employee
10,511 Views
Registered: ‎08-02-2007

Re: Xilinx Design Language

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Hi,

 

If you are interested to read a XDL file after converting from NCD refer 

http://www.fpgadeveloper.com/2011/06/how-to-read-an-ncd-file.html

 

If you would want to use Xilinx Design Language tutorial, refer 

http://www.mn.uio.no/ifi/english/research/projects/cosrecos/publications/paper/recosoc11beckhoff.pdf

 

http://www.ee.unlv.edu/~selvaraj/ecg707/lecture/Xilinx%20Design%20Language.pdf

 

 

--Hem

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Contributor
Contributor
10,496 Views
Registered: ‎04-24-2013

Re: Xilinx Design Language

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hi

      Hem, do you  know how to generate the .XDL file like the http://www.ee.unlv.edu/~selvaraj/ecg707/lecture/Xilinx%20Design%20Language.pdf used.

 

thanks!

 

handoujack.

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Xilinx Employee
Xilinx Employee
10,491 Views
Registered: ‎08-02-2007

Re: Xilinx Design Language

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Hi,

 

Ofcourse, type the command xdl in the command line suite as shown here.

 

xdl_capture.png

 

--Hem

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Scholar brimdavis
Scholar
10,481 Views
Registered: ‎04-26-2012

Re: Xilinx Design Language

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@handoujack : "does anybody knows the Xilinx Design Language(XDL)"

 

Xilinx's original XDL documentation can be found in certain older versions of ISE/Webpack.

Download and install a copy of ISE WebPACK 6.3i from here:
http://www.xilinx.com/webpack/classics/wpclassic/

Then take a look at the files in %XILINX%\help\data\xdl

-Brian

Contributor
Contributor
10,445 Views
Registered: ‎04-24-2013

Re: Xilinx Design Language

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I use the command (ISE6.3):xdl –ncd2xdl test.ncd test.xdl, and the xdl file is different from the “The Xilinx Design Language (XDL):Tutorial and Use Cases” described.

Why is my xdl file different from the file mentioned in “The Xilinx Design Language (XDL):Tutorial and Use Cases”?

 

Thanks!

 

Handoujack.

 

 

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Visitor pospij5
Visitor
8,673 Views
Registered: ‎07-15-2014

Re: Xilinx Design Language

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Hi, what is the difference? Do you use the same part as they use in the tutorial? Some naming conventions seem to be different for different parts...

@brimdavis: thanks for the link to old versions - finally I have also an "official" documentation;)

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Visitor sb_cse
Visitor
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Registered: ‎06-27-2016

Re: Xilinx Design Language

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Does anybody know how to generate Xilinx Design Language file for a FPGA interconnect resources using C or C++ language?

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Scholar markcurry
Scholar
728 Views
Registered: ‎09-16-2009

Re: Xilinx Design Language

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The XDL file format has no relevance to today's FPGA designs.  Why do you think you need it?

The format was barely needed in some weird design flows in the ISE days.  (I don't think I ever used it outside of some PlanAhead tutorials).  I don't think the file format is used in Vivado at all.

Can you give us ideas on what you're trying to accomplish?

Regards,

Mark

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Visitor sb_cse
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Registered: ‎06-27-2016

Re: Xilinx Design Language

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Hi, I am trying to generate routing path which is a collection of subsequent PIPs and Wire segments (Interconnection resource) based on some algorithm. I want to write C code for this path generation problem which will give the output in XDL format.

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Visitor sb_cse
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Registered: ‎06-27-2016

Re: Xilinx Design Language

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can anybody please tell how many single, double, long, pent , hex lines are there in virtex 6 and virtex 7?

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