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Observer
Observer
6,889 Views
Registered: ‎08-20-2007

XilinxCoreLib usage without Core Generator

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Has anyone used XilinxCoreLib without the GUI of the Core Generator? is it possible just to structurally connect components directly from the XilinxCoreLib? I tried to import XilinxCoreLib in my VHDL file but I faced various problems.
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Teacher
Teacher
7,837 Views
Registered: ‎08-14-2007

Hi,

you can use the models of the XilinxCoreLib, but only for simulation.

You can set the generics of the instantiated models according to the informations from the datasheet.

Be aware that parameters from the datasheet are not always corresponding "1-to-1" with the generics, and that some generics lack documentation.

That's because the datasheets are made to meet the coregen GUI.

 

You definitely can not use these models for synthesis. 

The CoreGen synthesis modules are presynthesized (and relative placeable) netlists.

 

To understand this you may inspect the files that are generated for a coregen module.

You will find an *.edf file, which is the EDIf netlist of the core.

And you will find some *.vhd or .v file which instantiates the wrapped XilinxCorelib module for Simulation.

The Project manager handles the swapping of these files automatically when you use the *.xco file there.

 

See the synthesis report (look for black boxes) and the *.fdo file to understand how this works.

 

Have a nice simulation

  Eilert 

 

 

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Teacher
Teacher
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Registered: ‎07-09-2009

Hi

 

can I ask why you would want to ?

 

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Teacher
Teacher
7,838 Views
Registered: ‎08-14-2007

Hi,

you can use the models of the XilinxCoreLib, but only for simulation.

You can set the generics of the instantiated models according to the informations from the datasheet.

Be aware that parameters from the datasheet are not always corresponding "1-to-1" with the generics, and that some generics lack documentation.

That's because the datasheets are made to meet the coregen GUI.

 

You definitely can not use these models for synthesis. 

The CoreGen synthesis modules are presynthesized (and relative placeable) netlists.

 

To understand this you may inspect the files that are generated for a coregen module.

You will find an *.edf file, which is the EDIf netlist of the core.

And you will find some *.vhd or .v file which instantiates the wrapped XilinxCorelib module for Simulation.

The Project manager handles the swapping of these files automatically when you use the *.xco file there.

 

See the synthesis report (look for black boxes) and the *.fdo file to understand how this works.

 

Have a nice simulation

  Eilert 

 

 

View solution in original post

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Observer
Observer
6,855 Views
Registered: ‎08-20-2007

Thank you eilert for your reply.

 

drjohnsmith, I wanted to use these models to automatically generate their parameters with a Python script and produce ready to synthesize components, but from what eilert says, this is not possible.

Message Edited by vlogaras on 03-09-2010 04:49 AM
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