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sgilbertson
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Registered: ‎01-05-2012

Zynq, 3x VDMA, ACP and HP0, ERROR: [BD 41-971] Segment <...> mapped into <...> at 0x00000000[ 1G ] overlaps with

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I have:

  • Zynq
  • Block diagram in Vivado 2017.2
  • ACP and HP0 slave AXI interfaces (I've also tried with ACP + HP0 + HP1)
  • Three VDMA blocks. One writes to RAM through ACP and the other two read from RAM through HP0. They all need to access the same address space in RAM.

I run connection automation, and I get automatic address mappings like:

HDMI_VDMA					
Data_MM2S (32 address bits : 4G)					
M_AXI_MM2S					
processing_system7_0	S_AXI_HP0	HP0_DDR_LOWOCM	0x0000_0000	1G	0x3FFF_FFFF
SAMPLE_DMA					
Data_S2MM (32 address bits : 4G)					
M_AXI_S2MM					
processing_system7_0	S_AXI_ACP	ACP_DDR_LOWOCM	0x0000_0000	1G	0x3FFF_FFFF
Video_DMA					
Data_MM2S (32 address bits : 4G)					
M_AXI_MM2S					
processing_system7_0	S_AXI_HP0	HP0_DDR_LOWOCM	0x0000_0000	1G	0x3FFF_FFFF

Note that all three define the same 1G address space starting at zero.

 

I run a design validation on the block diagram, and I get:

ERROR: [BD 41-971] Segment </processing_system7_0/S_AXI_ACP/ACP_DDR_LOWOCM> mapped into </HDMI_VDMA/Data_MM2S> at 0x00000000[ 1G ] overlaps with </processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM> mapped at 0x00000000[ 1G ]

What it says is true, in that there are two slaves (the ACP and HP0 interfaces on the PS7) mapped to the same address space, but since they have different masters surely that's allowed, isn't it?

 

How do I get my three VDMA blocks to pass validation so I can generate a bitstream?

 

 

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sgilbertson
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Registered: ‎01-05-2012

I was able to get it working. I think what made it work was actually unmapping unused address spaces, rather than excluding them. In case anybody is interested, attached is the modified test BD. In this version I also split the VDMAs so I'm using three AXI ports (ACP, HP0, HP1), but doing just that did not make it pass DRC.

 

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sgilbertson
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Registered: ‎01-05-2012

I made a simple BD that exhibits the problem. Attached is the test BD, exported (so do Tools/Run TCL Script to recreate the BD). Again this is Vivado 2017.2.

 

In addition to the original validation error about overlapping memory spaces, it produces a few more.

 

 

ERROR: [BD 41-703] Peripheral </SAMPLE_DMA/S_AXI_LITE/Reg> is mapped into master segment </SAMPLE_DMA/Data_S2MM/SEG_SAMPLE_DMA_Reg>, but there is no path between them. This is usually because an interconnect between the master and the peripheral has become misconfigured. Check and reconfigure the interconnect, or delete the master segment.
ERROR: [BD 41-703] Peripheral </Video_DMA/S_AXI_LITE/Reg> is mapped into master segment </SAMPLE_DMA/Data_S2MM/SEG_Video_DMA_Reg>, but there is no path between them. This is usually because an interconnect between the master and the peripheral has become misconfigured. Check and reconfigure the interconnect, or delete the master segment.
ERROR: [BD 41-971] Segment </processing_system7_0/S_AXI_ACP/ACP_DDR_LOWOCM> mapped into </HDMI_VDMA/Data_MM2S> at 0x00000000[ 1G ] overlaps with </processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM> mapped at 0x00000000[ 1G ]

 

The third of those errors is the one I originally reported. I don't know why the other two are happening in the little test BD but not in my main one. I read somewhere that it means you have an AXI4 master connected to an AXI3 slave, but the interconnect and AXI SmartConnect should take care of that.

 

This BD contains just the bare minimum to connect the three VDMA blocks to the PS7 core using ACP and HP0.

 

I hope this helps somebody figure out what I need to do to make it pass validation. Thanks.

 

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sgilbertson
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Observer
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Registered: ‎01-05-2012

I was able to get it working. I think what made it work was actually unmapping unused address spaces, rather than excluding them. In case anybody is interested, attached is the modified test BD. In this version I also split the VDMAs so I'm using three AXI ports (ACP, HP0, HP1), but doing just that did not make it pass DRC.

 

View solution in original post

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