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Visitor
Visitor
7,988 Views
Registered: ‎08-17-2012

add source error in ISE 12

Hi,

 

Whenever I try to add a *.v source file into an ISE project, there is an error: 

 

*.v is already in the project it cannot be added again. If the file does not appear as expected in the design hierarchy, you may need to change the view association in the Files panel.

 

But in the Files panel it states: View Association = All.

 

What is wrong with it?

 

Thanks

Senmeis 

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Xilinx Employee
Xilinx Employee
7,985 Views
Registered: ‎04-16-2012

Hi,

 

As error states, you had already added the *.v file to the project. To confirm this, click on "Files" tab in the left pane of project navigator window.

 

If the file is present and not shownup in the hierarchy, check the instantiation in the top module.

 

Thanks.

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Professor
Professor
7,977 Views
Registered: ‎08-14-2007

Normally if you add a verilog file to your project and associate it to "all" or "synthesis" it will

show up in the hierarchy pane whether or not it has been instantiated into the top level.

However if there is a serious syntax error, it won't show up if the parser cannot make out

that it actually contains a module definition.  This could happen if you forgot a `endif

to a `ifdef for example.  Unfortunately, when the file is not in the design hierarchy it becomes

hard to run a syntax check on it...

 

-- Gabor

-- Gabor
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