01-25-2019 04:04 AM
I want to integrate my design into the block diagram with Vivado 2018.3. There are two possible appoaches.
1) Add as a module to the block diagram and connect each signal of the master APB IF of the bridge to the corresponding signals of the module.
The tools complain that the address range of the APB master is not mapped ? Is there any way to add the address mapping this manually ?
2) Create an IP core from the design
Tried to create an address map for the APB IF, but not sure how to do it. I am aware of UG1119, but the memory mapping part is skipped in this document. Is this correct in the screen shot below ? How do I enter the range ? Is there any other document or example I can look at ?
I can connect this IP core easily to the APB master, but no address mapping information is propagated from the IP core to the bridge.