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Voyager
Voyager
114 Views
Registered: ‎06-26-2015

auto concatenate io port

is there an auto concatenate or easy way to concatenate bunch std_logic/single bit signal into a large bus in VHDL or verilog?

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4 Replies
Xilinx Employee
Xilinx Employee
66 Views
Registered: ‎05-22-2018

Re: auto concatenate io port

Hi @s002wjhw ,

 

I guess what you are looking for is configuring IO ports, if yes please check page no.36 of below link:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug899-vivado-io-clock-planning.pdf

Thanks,

Raj Singh.

 

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Xilinx Employee
Xilinx Employee
52 Views
Registered: ‎01-30-2019

Re: auto concatenate io port

Hi @s002wjhw 

please see the concat IP present on the page 29 of the following document.

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug994-vivado-ip-subsystems.pdf#page=29

Suraj C 

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Scholar dpaul24
Scholar
48 Views
Registered: ‎08-07-2014

Re: auto concatenate io port

@s002wjhw,

is there an auto concatenate or easy way to concatenate bunch std_logic/single bit signal into a large bus in VHDL or verilog?

In VHDL the simplest way would be to declare an array and use it. The array would constitute your 'bunch of signals'. For individual use you have each signal represented as bunch_signal(#).

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Scholar drjohnsmith
Scholar
45 Views
Registered: ‎07-09-2009

Re: auto concatenate io port

regarding using an array as ports,

  be aware, that till recently, VHDL, an array had to be all, input, output , or bi  ,

     There are other optoins, like dleayed enumeration, generics ,

  let us know a bot more as to what you want to do .

 

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