10-16-2019 08:46 AM
is there a tool or something that can auto generate a wrapper to reduce the IO for sythesis? i have some IP that has alot IO, but i want to test it on FPGA before attached those IO to other ips. usually i manually create a wrapper, mux the IO to reduce it so its sythesiszble. but i like to know if there is tool or ways using python/c++ to auto create a vhdl/verilog wrapper just to reduce the IO.
10-16-2019 11:57 PM
Check the following AR where you can set the unused IO as a virtual IO.
10-17-2019 01:36 AM
A technique we use is to make a wrapper of the module, and connect virtual IO modules from the IP store.
10-17-2019 12:42 PM
the issue is some ip i'm testing has thousands IO, which wont fit the FPGA i'm using. These IP will eventually be tie to other IPs, but for now i like to get it synthesis/P&R. So i create a wrapper to reduce those IO in order to fit the FPGA, but if there is some tcl script or other method that can do it without manually crating a wrapper, that'll be great.
I guess ill try the virtual io see if it works.
10-18-2019 12:43 AM
Experiance has shown that Xilinx belive TCL can do anything,
but I dont know of any off the shelf script to do what you want,
10-18-2019 12:46 AM
Ive just remembered, if you rusing the proper language ( VHDL of course )
have a perl script on line to create a test bench, this might be a usefull start ?
Lot sof ifs there, but it might be of use.