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Voyager
Voyager
271 Views
Registered: ‎06-26-2015

auto wrapper generation?

is there a tool or something that can auto generate a wrapper to reduce the IO for sythesis?  i have some IP that has alot IO, but i want to test it on FPGA before attached those IO to other ips.  usually i manually create a wrapper, mux the IO to reduce it so its sythesiszble.  but i like to know if there is tool or ways using python/c++ to auto create a vhdl/verilog wrapper just to reduce the IO.

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5 Replies
Moderator
Moderator
215 Views
Registered: ‎01-16-2013

Re: auto wrapper generation?

@s002wjhw 

 

Check the following AR where you can set the unused IO as a virtual IO. 

https://www.xilinx.com/support/answers/58609.html

 

--Syed

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Teacher drjohnsmith
Teacher
196 Views
Registered: ‎07-09-2009

Re: auto wrapper generation?

A technique we use is to make a wrapper of the module, and connect virtual IO modules from the IP store.

 

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Voyager
Voyager
166 Views
Registered: ‎06-26-2015

Re: auto wrapper generation?

the issue is some ip i'm testing has thousands IO, which wont fit the FPGA i'm using.  These IP will eventually be tie to other IPs, but for now i like to get it synthesis/P&R.  So i create a wrapper to reduce those IO in order to fit the FPGA, but if there is some tcl script or other method that can do it without manually crating a wrapper, that'll be great.

I guess ill try the virtual io see if it works.

 

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Teacher drjohnsmith
Teacher
141 Views
Registered: ‎07-09-2009

Re: auto wrapper generation?

Experiance has shown that Xilinx belive TCL can do anything,

    but I dont know of any off the shelf script to do what you want,

 

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Teacher drjohnsmith
Teacher
135 Views
Registered: ‎07-09-2009

Re: auto wrapper generation?

Ive just remembered, if you rusing the proper language ( VHDL of course )

 

then

https://www.doulos.com/knowhow/perl/testbench_creation/

have  a perl script on line to create a test bench, this might be a usefull start ?

Lot sof ifs there, but it might be of use.

 

 

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