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block design script - question about 'excluding' message in log

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Scholar
Posts: 1,272
Registered: ‎10-10-2014
Accepted Solution

block design script - question about 'excluding' message in log

I used 'write_bd_tcl' to save a tcl script that recreates my block diagram

 

when I run the tcl script, I can see the following in the vivado.log file right before the bd is save :

 

Excluding </snap/axi_dma_0/S_AXI_LITE/Reg> from </snap/axi_dma_0/Data_MM2S>
Excluding </snap/axi_gpio_0/S_AXI/Reg> from </snap/axi_dma_0/Data_MM2S>
Wrote  : </home/zynqdev/Zynq/2015_4/zynqsnap_test2/zynqsnap_test/zynqsnap_test/zynqsnap_test.srcs/sources_1/bd/design_1/design_1.bd> 

Now I'm wondering what these 2 lines 'excluding' mean ...? 

 

 

** kudo if the answer was helpfull. Accept as solution if your question is answered **

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Moderator
Posts: 3,319
Registered: ‎11-09-2015

Re: block design script - question about 'excluding' message in log

Hi @ronnywebers,

 

See Exclude segment from UG994:

exclude.PNG

 

Basically this is when you have an interconnect with multiple master. Some master do not need to access some slave so the slaves are excluded from the mapping of this particular master

-> I don't know if what I am writing is clear... let me know if not.

 

Hope that helps,

 

Regards,

 

Florent

Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Don't forget to reply, kudo, and accept as solution.

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Moderator
Posts: 3,319
Registered: ‎11-09-2015

Re: block design script - question about 'excluding' message in log

Hi @ronnywebers,

 

See Exclude segment from UG994:

exclude.PNG

 

Basically this is when you have an interconnect with multiple master. Some master do not need to access some slave so the slaves are excluded from the mapping of this particular master

-> I don't know if what I am writing is clear... let me know if not.

 

Hope that helps,

 

Regards,

 

Florent

Florent
Product Application Engineer - Xilinx Technical Support EMEA
------------------------------------------------------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
Scholar
Posts: 1,272
Registered: ‎10-10-2014

Re: block design script - question about 'excluding' message in log

ok - so I see this is because I have DMA controllers in my design :

 

dma addr exclude.png

 

for snap/axi_dma_0 there are 2 exclude segments, these match with the 2 lines in the Vivado.log file. I think block automation has created this for me, 'cause I don't remember adding this manually.

 

it's strange though that snap/axi_dma_1 does not have these exclude segments, probably that the block automation missed these? And also, besides the axi_gpio_0 and axi_dma_0 there are some other AXI IP's that could probably be excluded. 

 

I understand from UG884 that this is optional / a choice in my design, to prohibit that the DMA accidentally accesses other AXI IP, as it only needs to stream fifo data to DDR3 memory, and nothing else (?)

** kudo if the answer was helpfull. Accept as solution if your question is answered **
Moderator
Posts: 3,319
Registered: ‎11-09-2015

Re: block design script - question about 'excluding' message in log

Hi @ronnywebers,

 

for snap/axi_dma_0 there are 2 exclude segments, these match with the 2 lines in the Vivado.log file. I think block automation has created this for me, 'cause I don't remember adding this manually.

> Do you have this in your original BD? It was maybe done when auto-assigning addresses

 

it's strange though that snap/axi_dma_1 does not have these exclude segments, probably that the block automation missed these? And also, besides the axi_gpio_0 and axi_dma_0 there are some other AXI IP's that could probably be excluded. 

> Yes this is a bit strange. I cannot find a reason

 

I understand from UG884 that this is optional / a choice in my design, to prohibit that the DMA accidentally accesses other AXI IP, as it only needs to stream fifo data to DDR3 memory, and nothing else (?)

> I guess yes... (I have never used it...)

Florent
Product Application Engineer - Xilinx Technical Support EMEA
------------------------------------------------------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.